For leadless parts, the magic is in the method.
Solder dip or float testing is often used in the industry as it is quick, simple and cheap. But, it can lead to incorrect solderability assessments.
As seen in FIGURE 1, the solderability of the terminations was good, but the test method for this type of a bottom termination component (BTC) is not appropriate.
These process indicators on QFNs could suggest maintenance is needed.
The image in FIGURE 1 shows tin plating slivers on the body of a QFN component. During introduction, we have experienced slivers between the terminations by as much as 50%. FIGURE 2 shows burrs on the terminations, which are not uncommon but are again an indication of poor manufacturing quality control.
The wrong tool, or wrong procedures, is typically to blame.
Crimping is a reliable process, provided design and process engineers follow the crimp supplier’s guidelines on crimp wire capacity and the crimp tool settings. Both of these points would have prevented these horror stories. In recent years, good inspection and in-process control of the wire and cable preparation has been enhanced with the launch of IPC/WHMA-620, “Requirements and Acceptance for Cable and Wire Harness Assemblies.”
From discussions with those responsible for calibration, certification and approval of crimping, it is easy to see what can go wrong. When correct procedures are followed, crimps are extremely reliable, but when production does not want to buy the right tools, calibrate equipment or train staff, it can go wrong. Big time.
An insufficient bond between copper layers can lead to electrical test failure.
Delamination of printed circuit boards is typically associated with large blisters or bubbles in the board after soldering, but there are different examples of this phenomenon. The examples in FIGUREs 1a and b show via popping after reflow soldering, also known as “copper via rivet.”
In the images, the through via has elongated as the board expanded during heating. As layers in the multilayer board delaminated, further strain was placed on the copper plating until failure occurred. The board did fail electrical test, but the only problem visible on the surface of the board was the cracking of the solder mask, which can clearly be seen.
Solve capillary issues by increasing solids content.
It is very important to control conformal coating thickness on a printed board assembly. Problems with coating over different surfaces, particularly sharp corners that can lead to shorts from tin whiskers, have been demonstrated many times.
FIGURES 1 and 2 show capillary action on an SOIC and QFP, respectively, where the thickness of the coating is much higher around the leads and the body of the devices. With very high fluidity and spray coating, liquid capillaries under the package are starving the area of the board close to the edge of the pads.