Producing more boards per hour within the same line footprint is the ambition of every high-volume electronics assembly company. The more high-yield boards that can be squeezed out of the SMT line, the more profitability can be squeezed out of the bottom line.
Despite the provocative headline, this column is not a rant about how much I despise defects or the havoc they wreak on yields and profits; that’s already well established! Rather, this month’s space will focus on dedicated tooling and print platform vacuum control.
Recently our company developed some new test printed circuit boards that push the boundaries of today’s technology. These boards – very similar to what one would imagine a smartphone board would look like – are four-up, panelized 250 x 120mm boards packed with several leading-edge components, including metric 0201s and 0.25mm CSPs. As a process engineer who thrives on future technologies, this is really exciting stuff for me.
As our team was developing the print program for these little gems, we weren’t getting anywhere fast in terms of alignment. With features this small, there is absolutely no room for error, and the tolerances for the board and the stencil leave little wiggle room. Add in inevitable board stretch (discussed in a previous column) and, well, it was an exercise much like nailing jelly to a wall: it just wouldn’t stick. One part of the board would be absolutely bulls-eye, but then panel #4 would be out of alignment. When panel #4 was acceptable, then panels #2 and #3 were off. Why? Because there is this blasted thing called Theta!
In my experience, most customers just want to focus on standard x and y alignment. In all fairness, for larger pitches like 0.4mm CSPs, aligning for x and y is usually fine. But, with these highly miniaturized devices, rotation absolutely has to be factored in to accommodate for the ultra-fine pitches and board stretch (and sometimes stencil stretch as well). Using x and y only probably won’t get you there, and that’s certainly what we found with our new test boards. To address the challenge, we used a three fiducial capture software functionality. Using three fiducials, even though it may take a bit more time, ensures true triangulation because three points are now known. There is much better alignment and better rotational alignment as well. The minor time sacrifice will be worth it in the end.
Three fiducials, however, probably won’t be the end of the alignment story with finer-featured devices, and you’ll still be hammering away at that jelly. For this product, all the alignment options in our print platform’s software had to be used. In addition to three fiducial capture, we relied on experience with semiconductor printing and the technique used for wafer bumping. The rule with wafer bumping is to first sort out the rotation and not worry about x and y. If there is any mismatch of the artwork on the board to the stencil, find a happy medium where everything is off by the same amount. Once that’s done and rotation is defined, it’s a simple case of dialing it in to x and y. Too often, process engineers will try to do x and y and then rotation or, worse still, all of it together.
Of course, there may be the case where the board stretch is just too great and simply cannot be properly aligned to the stencil, particularly with highly miniaturized devices. In fact, robust SPC tools can flag boards that are outside of tolerance. The software takes data from the fiducial capture, measures board stretch and can issue an alarm if the tolerance is outside of the specified range. The reality is that board stretch has been accepted because there is some give in the process with larger (relatively speaking) components. But, things are getting really tight – as evidenced by our recent test board experience – and the give is giving way. With the tools we used, good alignment is certainly achievable, and frankly, it’s what will have to be done for sub-0.3mm CSPs and the like. You have to deal with the cards you’re dealt, and right now that means some board stretch. As I noted in a previous column, though, PCB manufacturers will have to solve the board stretch issue as the industry migrates to these smaller devices – and it’s not far off. Otherwise, we’ll be looking at processing singulated PCBs.
As far as alignment goes, the vast majority of manufacturers today are only doing x and y offsets, and for current technology, that should be satisfactory. But I caution anyone reading this column to brush up on their platform’s capabilities and understand how to use rotation and multiple fiducial capture. Without question, 0.25mm CSPs are on their way, and you don’t want to be nailing jelly to a wall.
Clive Ashmore is global applied process engineering manager at DEK International (dek.com); firstname.lastname@example.org. His column appears bimonthly.