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Zurich, Switzerland -- DEK has developed a high-throughput backside wafer coating process, which is hosted on a mass imaging platform capable of exceeding the +/- 12.5 um total thickness variation (TTV) required by most wafer processing specialists. The process is compatible with underfill or adhesive-type coatings which are normally applied at a nominal 50 m thickness to the backside of semiconductor wafers prior to singulation.

“For any backside wafer coating process, TTV is the critical success factor,” said Clive Ashmore, global applied process engineering group manager. “With this latest application advancement, we are helping semiconductor packaging manufacturers increase throughput and reduce the cost per package by using high accuracy mass imaging.”

According to the company, the use of an optional wafer handler, flexible printing platform and reflow oven achieves more flexibility than dedicated backside coating machines. The system can be re-deployed for other processing requirements.

The backside wafer coating process is compatible with the company’s metal stencil and emulsion screen technologies. Metal stencils enable materials with larger filler particles, such as encapsulation materials, to be applied with a totally smooth surface finish. Mesh stencils allow other materials such as thermoplastic adhesives to be deposited accurately and at high speed. In each case, the capabilities of the machine and stencil technology are key to achieving control over the print thickness and ensuring uniformity at high volumes.

DEK, dek.com

Launched at the Semicon Europa show in April, two of the LDS3300 C models have already been delivered to the North American fab of a major semiconductor manufacturer. Additonal installations for this client are expected soon in European facilities.

“Conceived for perfect integration into automated fab lines, our new system combines micro and macro defect detection for all 300-mm wafer applications,” said Thomas Breser, strategic marketing & communications director. “This is an important part of why our client chose the LDS3300 C.”

As part of the automated macro inspection process, provides automated reticle and fuse inspection capabilities. High throughput (up to 130 wafers/hour) helps increase yield and reduce cost of ownership.

Focal plane analysis has high accuracy and efficiency in scanner focus calibration and monitoring, and scanner e-chuck flatness measurement and monitoring.

Leica Microsystems, leica-microsystems.com

Ashburn, VA – Zestron’s VIGON A 200 recently passed extensive surface insulation resistance (SIR) testing conducted in accordance with J-STD 001.

To conduct the testing, an IPC B24 test comb structure was cleaned with the water-based cleaning agent in a spray-in-air process. During the four-day procedure, the climatic storage temperature was calibrated at 77^oF / 25^oC, while the relative humidity was set at 60%. The test comb’s SIR values were continuously monitored and were reportedly consistently well-above the required 100 ΜΩ. Further inspection did not reveal any dendrites or corrosion effects.

The cleaner is designed to remove flux residues from electronic assemblies.

For complete results of the testing, contact the Application Technology Department at (888) 999-9116.