Progress for glass-core substrates and RDL interposers highlighted ECTC’s 75th anniversary conference.

More than 2,500 attendees braved the stormy Texas weather to discuss the latest developments in packaging and assembly at the IEEE Electronics Components and Technology Conference (ECTC) in May. Among the many presentations were a number focused on high-performance packaging, with clear momentum for expanded use of molded redistribution layer (RDL) packages, wafer-level packaging and updates on the states of glass core substrates. IBM announced its license of Deca’s RDL technology and outlined production plans for North America. Many presentations described progress in hybrid bonding and co-packaged optics, while others highlighted thermal challenges and metrology needs.

Tuesday featured overlapping special sessions and a full day for the Heterogeneous Integration Roadmap workshop. One special session focused on ultra-high density interconnect technologies and supply chain readiness for AI and HPC, with panel members from Unimicron, Applied Materials, Atotech, Ajinomoto, Onto Innovation and ORC. Concurrently, another special session discussed hybrid bonding and the needs and challenges for the next decade. That panel included Samsung Electronics, AMD, KLA, IMEC, Toray Industries and Adeia, emphasizing the need for improved metrology capabilities and tools.

A special session covered quantum photonic advanced packaging with panel members from Senko, Air Force Research Labs, NTT and Quantum Technologies. Another special session included panel members from AIM Photonics, Tyndall Institute, Intel and Rensselaer Polytechnic Institute, who discussed quantum photonics advanced packaging. Representatives from ASE, IBM, Ericsson, IMEC and Penn State University discussed advancements in mmWave and sub-THz packaging along with failure analysis in heterogeneous integration during a special session. The special session on advancements in chiplets focused on fault isolation and failure analysis sin heterogeneous integration, with panel members from ASE, Sigray, AMD, TaraView, University of Florida and Zeiss. Panelists from IBM, Georgia Tech, IMEC and Peking University addressed thermal management solutions for next-generation backside power delivery.

During the special session on glass core versus RDL interposers, panel members from AMD, TSMC, Intel, SEMCO, FICT and Toppan participated. TSMC reminded the audience that packages with RDL have been in production for more than 10 years and highlighted the electrical performance, stable yield, large process window, reduced stress on microbumps and excellent reliability. AMD explained that glass panels offer the potential for mechanical stability (flatness, low and tunable CTE, low warpage).

Intel, FICT, SEMCO and Toppan highlighted the need for glass-core substrates with a low CTE core to reduce substrate warpage for large body size packages and shared their progress. FICT described its process for stacking multiple glass-core layers with paste in a single lamination step. Intel discussed its demonstration with several build-up layers and 1:20 aspect ratio through-glass vias (TGVs) in the core, calling for the industry to develop the glass package ecosystem. SEMCO described development of build-up layers on a glass core with 40µm laser-fabricated TGVs.

Toppan described its work in glass-core packages, glass interposers and glass interposers with RDL. Respective challenges include back cracking (seware) and second-level reliability for glass core, as well as the supply chain. Later in conference presentations, Unimicron discussed the issue with low CTE glass and the need to use higher CTE glass core for board-level reliability. Shinko Electric’s paper also highlighted challenges with low CTE glass. Dai Nippon Printing (DNP) analyzed thermal stress on TGVs and showed the progress with TGVs using stress relief provided by a resin interface in the vias. DNP reported samples passed 1,000 hours of testing at temperatures ranging from -55° to 150°C, featuring an 80µm via diameter in a 400µm-thick glass core. DNP also provided a transmission performance evaluation for glass substrates with 2µm lines and spaces.

Organizations, including AGC with University of Tokyo, Corning, Ulvac, Uyemura and Purdue University, highlighted their progress in fabricating TGVs. DuPont discussed use of a new dry-film dielectric material for glass-core substrates. Disco compared post dicing die strength for different singulation methods used for glass core substrates. EOSL presented modeling results of TGV mechanical reliability of substrates under annealing conditions. Georgia Tech presented research modeling of glass-core packages with embedded dies.

A Tuesday special night session featured comments from AMD, ASRA in Japan, NTT, Qualcomm and Marvell, providing user perspectives on chiplet technology. A startup innovation challenge competition featured pitches from Micro Qusar Tech, Scrona, EuQlid, Photonect and ICSPI.

AMD’s keynote by Sam Naffziger opened the conference Wednesday with the topic Achieving Efficient Zetascale Compute in the AI Era. He described increased demand for compute and the energy required to power it as one of the greatest industry challenges. He noted that power limits performance and that developers need to improve power delivery. AMD’s 3.5D approach decreases the energy cost of compute, permitting more silicon to fit in a smaller compute area. Communication efficiency is also key. Optical is expected to improve efficiency. AMD aims for high integration of memory and compute while lowering energy per bit.

Thursday morning’s plenary session focused on advanced power delivery for the AI computing era with panel members from Intel, ASE, Qualcomm, AMD and TSMC. Qualcomm noted that droop limits CPU/GPU/NPU performance. AMD indicated that power consumption doubles every two years while they only observe modest efficiency gains. Developers will commonly use integrated voltage regulators in the package. Several presentations at the conference discussed the use of integrated voltage regulators. Future systems will require liquid cooling.

High-performance packaging. Many presentations focused on new packages for high-performance packaging. Trends show larger packages exceeding 120mm x 120mm body size in the future. Managing warpage is a challenge and a variety of package options were presented. TSMC described its system-on-wafer (SoW-X) technology for next-generation AI servers, supporting up to 16 full-reticle ASICs plus 80 HBM4 stacks on a reconstructed 300mm wafer that incorporates RDLs and local-silicon interconnects (LSI) or bridges. Industry adoption of RDL interposers is clearly a trend. TSMC discussed package warpage reduction for large 110mm x 110mm CoWoS-R supporting up to four logic die plus 12 HBMs. Resonac described the process development and reliability of a 120mm x 120mm body size package, achieving lower warpage using a low melting point temperature bismuth solder. Alibaba described board-level assembly challenges and thermal interface material selections for large-size packages.

Intel presented its development of the embedded multi-die bridge (EMIB) substrate with bridge dies andTSVs targeted for large body packages, such as AI.

Hybrid bonding. More than 60 presentations focused on hybrid bonding developments, including wafer-to-wafer and die-to-wafer bonding processes, equipment and materials. Research included work from Toray industries, IME A*STAR, ITRI, National Yang Ming Chiao Tung University, Applied Materials, Sungkyunkwan University and BASF, Yokohama National University, Disco, STMicroelectronics, Samsung, IBM, Sony Semiconductor, ULVAC and LINTEC, Micron, Intel, UCLA, MacDermid Alpha Semiconductor Solutions, IMEC, Purdue University, Resonac, ETRI, EVG, Tohoku University, TEL and Japan’s WOW Alliance.

Photonics and co-packaged optics. Presentations increasingly focused on developments in photonics and co-packaged optics (CPO). IBM described its CPO test vehicle. Intel described its demonstration of CPO assembly for fiber-based optical interconnects. Celestial AI described an optical multichip bridge interposer assembly process for high-density photonic interconnects. Corning, Fraunhofer, IME A*Star and FICT described glass substrates targeted for CPO. TSMC presented optical and electrical characterization of its Compact Universal Photonic Engine (COUPE). Intel discussed the use of EMIB for CPO. Nvidia discussed optimizing costs, complexity and performance for CPO SMF arrays. Furukawa Electric described a 21-dBm per channel operation of a 16-channel CWDM ELSFP module under air-cooling conditions.

Sessions also covered topics such as antennae design and RF, automotive, additive technology, wearables and medical applications.

ECTC returns to Orlando in 2026.

E. Jan Vardaman is president of TechSearch International (techsearchinc.com); jan@techsearchinc.com.

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