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Features Articles

Mike Buetow

In the end, will the naysayers be proved right?

Multek in July announced it would open a major tech center in the Silicon Valley, performing critical research on everything from new materials and manufacturing processes to signal integrity. Multek president Franck Lize and CTO Dr. Bill Beckenbaugh discussed the Innovation Technology Center with PCD&F editor in chief Mike Buetow via phone.

MB: Has the ITC been in the works internally for some time?
FL: So the new center is very interesting. We spent the past four months with customers to understand what their requirements were for the next-generation products. With the telecom market, with the 4G and 5G, and even the consumer business with flexible products like wearables and the flexible phones that we hear about in the news, there’s a change (coming) in the PCB industry because there are different requirements for those PCBs.

Our customers need many more solutions now than ever in the past 20 years. Multek wants to be a pioneer here. The ITC is part of the solution that Multek is putting together.

MB: Is it a standalone entity?
FL: It’s part of a full system. We are co-located next to the big NPI center that Flextronics has in the Bay Area. We needed a place for knowledge and engineering, and we wanted to be in the best location in the world for electronics. But the ITC is much more than that. We are leveraging on our network of field applications engineers, which we have all over the world. Thanks to this extended network, our customers have direct access to this great capital of PCB and flexible circuit knowledge, no matter where in the world they are. It fits into the full Multek solution. Whether it’s a field application engineer or our top engineers in the Silicon Valley, we are working to provide early engagement for new materials, signal integrity issues, and new flexible designs. For any new challenges that our customers have, Multek helps them make the bridge between concept and actual manufacturing.

MB: We are seeing companies such as Agilent and IBM change their paradigms so that their design kickoff meetings involve everyone from the SI engineer to the hardware engineer, the firmware guy, the fabricator and the assembly process engineer. The DfM rules are hard-coded at that time, so that there are no changes down the line. What are you seeing insofar as this, and did it play into your decision about the ITC?
BB: This is the trend we are seeing over the past several years, and it’s why we wanted to move past our internal paradigm and turn it around so that the requirements and cost of the functions are designed in early, because if we don’t participate in it, we won’t be able to help the customer do a better job, but also because they might be doing something using an older technology than they need to, one that might cost them money or be less efficient.

We wanted to make it customer-focused and not limited, an open-ended ability to create a team and bring the right people with the right answers to the right problem set. It also helps us define our future capacity and technology requirements better.

MB: To what degree will ITC be involved in blue sky research outside of what’s directly needed by customers?
BB: Blue sky for us is defined for something that’s been coming, but traditionally we have put it in terms of the optimum solution for copper-based interconnects. At some point we will move to other ways to move to signal propagation. The future will be very different.

This industry has only gone through two or three revolutions in the past 25 years. We feel the next one is coming in the next few years. I don’t want to give too much about that because of the proprietary nature of it, but it is something we are working on.

MB: Bill, what are you seeing in terms of 3D packaging?
BB: Being located with the Product Innovation Center, we are able to provide the interconnect part to accelerate our Flextronics corporate roadmap, and provide a Multek interconnect solution for MEMs packaging. We are in mass production on product with package-driven interconnect pitches and component densities and assembly requirements. We see sensor integration and integration of MEMS devices is a key driver of the next generation of interconnect solutions. I’ve been in advanced packaging as part of my career and am very sensitive to it driving the next generation of electronics and PCB boards. It’s the key to the future of electronics growth.

MB: From the assembly viewpoint, we see issues where the tolerances for SMT assembly require bare board yields in the 98%, 99% range, and not just by visual inspection, or there are problems with printing. These problems will be even more severe with smaller components such as metric 0201s.
BB: You’re touching on the area that is exactly why we are co-located with our Flextronics Assembly Engineering Lab. Regardless of whether it’s a module, or a chip on a package, all require flawless assembly. From a Six Sigma standpoint, it’s necessary to fully control all the aspects of the process.

Ed.: For the full interview, visit http://bit.ly/14kfJOA.

As our alternative energy column comes to a close, the author contemplates the past and the future.

Boundary scan and embedded test will need to make up for ICT gaps.

Smaller component technologies on the horizon, and the mix of parts to be placed, will present severe demands on accurate solder paste deposition.

Stencil use leads to lower tension, and eventually misalignment. Is there a solution?

Anyone with even a modicum of understanding about the printing process knows that stencil (or screen) tension is integral to print integrity. While the amount of tension is important, what’s even more critical is that the proper tension is evenly distributed across the stencil. There is also some evidence that points to higher tension being more effective than lower tension, particularly for today’s finer-pitched devices and especially when there is an extremely high density of apertures. Take a stencil for one of today’s mobile phone printed circuit boards (PCB), for example. These stencils tend to have more holes than stencil, so tension is critical.

On average, tensions between 30 and 35 Newton are a good starting point for a properly tensioned stencil. If the tension changes over time – either from process use or post-process cleaning – the printing integrity will be affected. When apertures are filled, the board and the stencil come together like a sandwich. If the tension in any part of the stencil has diminished, as the print stroke begins, the stencil image moves and gets pushed away with the direction of the squeegee. As the apertures are being filled, there will be misalignment as the print stroke progresses and it becomes increasingly difficult to keep the print process in control.

When the board is released from the stencil, a well-tensioned stencil will produce a very controlled release. If the stencil has become baggy and less tense, the stencil will follow the board down with the table so, instead of a complete clean separation, some parts of the stencil will separate before others. In the high-density areas of the board – where there are many, many 0.4mm CSPs and hundreds of 0201s or 01005s – there is a large volume of solder paste that wants to stick on the apertures. This condition will tend to pull the stencil down, resulting in an uncontrolled release.

Traditionally, mesh mounted stencils have been the stencil architecture employed most frequently in electronics assembly. When using a metal mesh (as opposed to a polyester mesh) from which the stencil is suspended, extremely high tensions can be initially created. However, mesh mounted stencils tend to relax and lose tension as they are used and cleaned. Consider that the entire stencil is placed into the cleaning system that uses temperature and chemistry to clean off solder residues. Then, the stencil is dried with hot air. Cleaning and drying are inherently bad for the adhesive materials used to manufacture mesh mount stencils. This process results in varying coefficients of thermal expansion, which cannot only weaken the elasticity of the stencil and mesh, but can also cause the stencil image to shift. When processing fine-pitch devices, this is highly problematic.

So, what’s the solution? The best option would be to clean the foil only and preserve the integrity of the tension. This is precisely the idea behind many of the market’s frameless stencil tensioning systems. With these stencils, the foil is separate from the frame, which has many advantages. While some of these systems faced early challenges (operator injuries from sharp edges, for example), these obstacles have been overcome, and the popularity of frameless stencils has grown in recent years. There are many benefits to frameless stencil technology, including storage space savings, sustainability, lower costs over the long term and, most important, no loss of tension over time. The stencil foils are cleaned once removed from the frame, so there are no concerns about mesh or adhesive impacts. When placed into the frame, the foil is tensioned to the same level each time and, because there is no mesh to contend with, there is no loss of tension – even in high-volume manufacturing environments. In comparison, mesh mounted stencils used in high-volume processes need to be replaced an average of every two to four weeks.

In the past, frameless stencils provided tensions of 30 to 35 Newton, which was fine for standard SMT (0.5mm pitch and above) but not for today’s miniaturized devices. If using these systems for fine-pitch processes, a frameless stencil that can provide a tension of 40 Newton or greater is required for a robust process. Anyone considering a frameless stencil system needs to bear this in mind during the selection process.

The new challenges of miniaturization dictate now more than ever that stencil tension is consistent. Tighter pitches combined with thinner stencils and high-density apertures make stencil tension control and uniformity an increasingly critical parameter. In this case, tension is indeed a good thing.

Clive Ashmore is global applied process engineering manager at DEK International (dek.com); cashmore@dek.com. His column appears bimonthly.