White Papers

Joint Project for Mechanical Qualification of Next Generation High Density Package-on-Package (PoP) with Through Mold Via Technology

This paper will summarize joint work between ST Microelectronics, Amkor Technology and Nokia; to qualify Amkor’s through mold via (TMV™) bottom package technology for next generation high density PoP applications. The 12 x 12mm daisy chain test vehicle reported in this joint work includes a thin flip chip die in a fully molded bottom package with 516 bottom BGAs at 0.4mm pitch and 168 top solderable through mold vias at 0.5mm pitch. This paper will report the package level (moisture resistance, temperature cycling) and board level (temperature cycle, drop) qualification data against IC and handheld application requirements.

Additional data for package warpage control and board level reliability for larger PoP applications using TMV technology will be included beyond what was reported at ECTC 1, SMTA International 2 during 2008 and IMAPS Device Packaging 3 in March 2009, based on a 14 x 14mm daisy chain test vehicle with 620 bottom BGAs at 0.4mm pitch and 200 top vias at 0.5mm pitch. Additional data on the TMV technology will be provided including: maximum die to package size design benefits for wirebond, stacked and flip chip die, coplanarity and package warpage measured by shadow moiré across lead free SMT reflow profiles. JEDEC standardization work for next generation PoP applications will be provided for mechanical and high density electrical interface requirements driven by low power double data rate 2 memory (LP DDR2), in single and dual channel architectures which require 0.5 and 0.4mm pitch interfaces respectively. 4

Assembly and Reliability Assessment of Fine Pitch TMV Package on Package Components

Since their introduction, package on package components have proven popular, particularly in handheld portable applications. These packages offer significant advantages, including increased density through stacking of logic and memory devices in the same component footprint, and flexibility as a result of the assembler’s ability to select different memory devices for inclusion in the stack. Next generation versions of Package on Package devices are now emerging which offer improvements in component warpage during reflow and increased pin count due to pitch reduction on both the top and bottom package. This study focused on different assembly variations for a new 14 mm square package on package component with a 0.4mm pitch array on the lower package and 0.5mm pitch array on the upper package. This configuration allows for 620 I/O on the lower package, and 200 I/O on the upper package. The lower package in the stack featured a through mold via (TMV) structure, which reduces component warpage, and improves assembly yield. Flux Dip and Paste Dip were assessed for assembly of the upper package in terms of assembly yield, mechanical shock and thermal cycling reliability. Two different underfill materials were assessed for use on these components – one selected for optimal shock test performance, and one selected to optimize thermal cycling reliability. All assembly variations were subjected to accelerated thermal cycling (ATC) from -40°C to 125°C with a planned test duration of 2000 cycles. Mechanical shock testing was performed on a sub-set of the assembly variations to complete the reliability assessment.

Summary of the Final SEC Rules on Conflict Minerals

On August 22, 2012, the Securities and Exchange Commission (SEC) voted in favor (3-2) of a long-awaited final conflict minerals regulation. Overall, the final regulation addresses most of the concerns raised by IPC. Although compliance will still be a significant burden for the industry, the final rule is an improvement over the proposed rule.

Package on Package (PoP) Stacking and Board Level Reliability, Results of Joint Industry Study

Authors: Moody Dreiza, Lee Smith, Gene Dunn, Niranjan Vijayaragavan and Jeremy Werner

Abstract: This paper presents the results of a joint three-way study between Amkor Technology, Panasonic Factory Solutions and Spansion in the area of package on package (PoP) board level reliability (BLR). (BLR is also referred to as second level or solder joint reliability within the industry.) While PoP is experiencing exponential growth in handheld portable electronics applications, as reported by iSuppli and others, to date PoP BLR data has been customer specific and not available for industry publication. Significant company internal and industry data exists to help optimize designs for BLR performance in 0.5mm pitch, Pb free fine pitch BGA (FBGA) or chip scale packages (CSP). In addition new work has emerged in 0.4mm pitch CSP as reported by Scanlan, Syed, Sethuraman, et al. However, industry data specific to the reliability of the top to bottom PoP-BGA interface has been critical to designers in planning for new PoP applications or configurations. In addition, data was needed to validate whether current best practices for Pb-free reliability performance of bottom 0.5mm pitch BGA to mother board interface still applies in PoP stacked structures.

Published: March 23, 2006


Assembly and Rework of Lead Free Package on Package Technology

Authors: Raymond G. Clark and Joseph D. Poole

Abstract: Miniaturization continues to be a driving force in both integrated circuit packaging and printed circuit board laminate
technology. In addition to decreasing component pitch (lead to lead spacing), utilization of the vertical space by stack Save ing
packages has found wide acceptance by both designers and manufactures of electronics alike. Lead free Package on Package
(PoP) technology represents one of the latest advancements in vertical electronics packaging integration and has become the
preferred technology for mobile hand held electronics applications. TT Electronics in Perry, Ohio has developed the capability
to assemble and rework numerous “state of the art” packaging technologies. This paper will focus on the essential
engineering development activities performed to demonstrate TT Electronics’ ability to both assemble and rework PoP

Printing and Assembly Challenges for Quad Flat No-Lead Packages

Author: William E. Coleman, Ph.D.

Abstract: QFNs present several assembly problems. The QFN can float during reflow if there is too much solder. Aperture size is a problem because with aperture widths as low as 0.175mm and aperture lengths as low as 0.4mm there can be a problem with the percent of paste transfer. Another challenge is the type of solder mask that’s employed on the printed circuit board. The article explores three types of solder mask designs – SMD where the pad opening on the board is defined by the solder mask; NSMD, where the pad itself defines the boundary of the pad and the solder mask is pulled back off the pad (typically 0.05 to 0.075mm per side); and NSMD–Window – and gives stencil design considerations and guidelines for each type. QFN repair is also covered. It  shows how with proper stencil design, proper stencil technology selection (laser, electroform, and nano-coat), and proper PCB solder mask layout, the challenges that quad flat no-lead packages (QFNs) present to the assembly process can be overcome.

Released September 2012


Two Worlds Converging: Chipshooting and Flip-chip Bonding

By Eric Klaver and Patrick Huberts

Pick-and-place equipment has over the years mostly evolved in four key areas; it is faster, more reliable, more accurate and more user friendly. Most pick & place vendors have aimed at the mass production market, while others have moved towards more dedicated markets – mostly where production flexibility is needed as with high-mix, prototyping or evaluation. But in the end, we’re all doing the same thing: picking and placing components on bare substrates.

3 pages.





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