PALO ALTO and MOUNTAIN VIEW, CA, Dec. 14, 2004 -- Agilent Technologies Inc. and Synopsys Inc. have introduced a scan diagnostics reference methodology that speeds fault localization and failure analysis for semiconductor design and test engineers, the result of a three-year strategic alliance.

 

The methodology is enabled by the Agilent 93000 SmarTest Program Generator (PG) 2.2 and the Synopsys TetraMAX automatic test pattern generation (ATPG) solution, in conjunction with the Agilent 93000 SOC Series test platform. The tools automate the bidirectional information sharing between electronic design automation (EDA) and automatic test equipment (ATE) required for scan diagnostics.

 

As process geometries shrink and device complexity grows, identifying device failures becomes increasingly difficult. The demand for shorter time to market and lower product cost makes rapid diagnostics and fault localization vital during the first silicon evaluation and production ramp up. EDA companies have begun to offer fault localization tools, but they require failure information from automatic test equipment. Until now, a standardized and supported means for sharing information from ATE has not been available.

 

The SmarTest PG 2.2 offers a transition from the EDA environment to the capabilities of the 93000 SOC Series, which speeds test development for functional and scan tests. SmarTest PG 2.2 provides a scan failure map on the SOC Series in their native scan context, speeding first silicon debug. Features a simplified user interface and command-line operation, and supports industry-standard EDA input formats, including Standard Test Interface Language (STIL), Waveform Generation Language (WGL), Value Change Dump (VCD), Extended VCD (EVCD) and Core Test Language (CTL).

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