Design and test workflow reduces product development time for double-data rate dynamic random-access memory (DDR5 DRAM) systems.

Provides transmitter test methods to measure signal eye diagram after equalization; loopback bit-error-rate (BER) receiver tests to validate device and system reliability; logic analysis to debug DDR5 traffic transactions to identify source of system instability. Includes PathWave ADS Memory Designer for DDR5; is a simulation environment that addresses ability to predict performance, optimize design and perform virtual transmitter compliance test, before realizing first hardware prototype; reduces simulation setup time from hours to minutes with features such as DDR components, smart wires and intelligent memory probe; increases simulation accuracy for DDR5 by representing receiver equalization with IBIS algorithmic modeling interface (IBIS-AMI) models. Consists of modeling and simulation; probing and interposers; transmitter test with oscilloscopes and compliance software; receiver test fixtures; receiver test solution for loopback bit error rate testing; logic analysis; power rail probes.

Keysight Technologies


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