Tokyo and Santa Clara, CA — NEC Corp., NEC Electronics and NEC Electronics America today unveiled a new system-in-package (SiP) technology capable of stacking logic and gigabit-class memory in a single package to enable high-speed, high-definition image processing in mobile devices.

The technology, SMAFTI (SMArt connection with Feed-Through Interposer), features a 3-D chip connection whose approx. 60-micron gap and 50-micron-pitch microbump between the logic and memory devices can support transmissions up to 100 gigabits Gbps.

“The strong demand for digital video tv, digital video gaming and other digital video capabilities in portable consumer devices is driving the need for high-speed image processing that realizes crystal-clear resolutions,” said Takaaki Kuwata, general manager, Advanced Device Development Division, NEC Electronics. “SOC technologies present a disadvantage in terms of development cost and memory capacity, while conventional SiP products have larger package sizes due to thicker interposers, and have limitations in signal transfer speed, wire-bonding interconnections, and side-by-side chip placement. The new technology resolves these issues and enables engineers to effectively design and manufacture high-performance systems for mobile electronic devices.”

The technology leverages three key enabling technologies: a 50-micron-pitch microbump interconnection technology, a 15-micron-thick feed-through interposer (FTI) based on superconnect technology and a multichip assembly process.

The microbump interconnection realizes low power dissipation, a small form factor and high-speed interchip communication at more than 100 Gbps. Reduces the size of conventional pitch bumps and accommodates four times the number of bumps in the same area. Produces reliable high-speed data transfers.

Superconnect technology is used in chip fabrication and has a copper signal trace 15 microns wide and a polyimide layer 7 microns thick. Can convert a chip’s wiring pitch to 50 microns and fan out the pitch connection of an outer ball grid array to 500 microns. Routing of signals from a logic chip with a 50-micron pitch and memory connection points to universal substrate terminals can be simplified.

The multichip assembly process enhances existing wafer-based manufacturing processes typically used for SOCs. Memory chips are first mounted onto silicon wafers using wiring based on superconnect technology. Then the chips and wiring layer are molded by resin and the silicon wafer is removed. The BGA attachment process follows.