A good library is built with an understanding of the manufacturing limits.

One of the primary factors in the quality of a printed circuit board design system is the makeup of the component footprints. The board can only be as good as the foundational pieces. Making it up as you go along is not a process for the long term. Errors or inconsistencies in the library account for a fair share of the feedback we receive from the fabricator. That is the wrong time to consider the fundamental building blocks of our collective occupation.

The source of the component footprints should be considered. A good cross-section of the supply chain provides the customer with schematic and layout symbols. This is, of course, to make it easier for us to implement their chips and other parts. CAD tools often come preloaded with a number of device examples to get you started.

Take those "freebies" with a grain of salt. One of the ways this kind of help can get in the way is in terms of traceability. One of the more important aspects of a good library is to have one and only one instance of a particular part. Naming conventions come into play here. Many, but not all, of the baseline libraries use naming conventions outlined by IPC-7351.

The primary purpose of surface finishes is to prevent oxidation of the copper prior to soldering components.

Back when I held a soldering iron, we used a mixture of tin (63%) and lead (37%) for the solder (Sn63). The boards had the same coating on the plated holes and surface-mount pads. The application for surface mount is referred to as hot air solder leveling (HASL) and applies to any of the available solder types. The beauty of Sn63 is it has a lower melting point and is eutectic. “Eutectic” means the metal solidifies rapidly over a short temperature range. The benefit is fewer disturbed solder joints and good “wetting,” where the surface finish and the solder form a cohesive bond for a reliable connection. You can still buy Sn63 off the shelf at the local electronics store.

On the other hand, lead is a dangerous metal that can cause birth defects and other health issues. The Europeans took the vanguard with the RoHS initiative. If you want to sell electronics products to consumers, the lead content must be the minimum possible – not eliminated entirely but found primarily as a trace element within chips.

SAC (Sn-Ag-Cu): a heroic alloy. Metallurgists all over the world looked for replacement formulas. Tin is still viable and is generally mixed with small amounts of silver and other elements such as antimony, copper or bismuth. Tin makes up the bulk of the alloy, typically around 95% to 99.3%. If pure tin was used, the results could be problematic. Tin whiskers from dendritic growth present a shorting risk.

FIGURE 1. Pure, non-alloyed metals exhibit crystalline growth as the metal forms branches over time. Environmental conditions can aggravate the process. (Source: NTS Corp.)

Without lead, tin has a much higher melting point and does not solidify as quickly. The double-complication requires a dielectric material that can withstand the higher temperatures without breaking down.

The maximum working temperature of the material is one of the primary selling points. It is known as the glass transition (Tg) temperature. The materials we used in the old days did not stand up to the process, so the entire PCB material set had to be seriously upgraded. Going lead-free raised the reflow temperatures considerably. Boards and components alike have gone green since then.

Exemptions exist where tin-lead is still allowed. Spacecrafts that will eventually burn up on reentry are one such exemption. The goal of RoHS is to reduce the amount of lead that goes into the landfill. Provided the company can certify all its products will be returned to the factory for proper disposal, Sn63 coatings on the PCB are permissible. Obviously, consumer products do not get such an exemption.

ENIG: the gold standard. While tin-silver plating is still viable, the “gold standard” is gold. The mainstream alloy is immersion gold over electroless nickel over copper, or ENIG for short. The reason this is a preferred plating is the downstream process of assembly is more boring without the likelihood of tin whiskers. We like it to be boring when it comes to making goods. Those who study S-parameters also have a fondness for the consistency of ENIG finishes.

This plating is primarily aimed at high-density interconnect fabricators. The process can yield a solderable footprint with via-in-pad situations. Fine-pitch BGAs and other shrunken circuits require microvias. Plating with ENIG will likely improve yields due to the land patterns coming out flatter than with other types of plating. It’s also a go-to finish for flex circuits. It plays well with solder mask, making a good base for the following layer.

FIGURE 2. ENIG finish with through-hole vias and surface-mount components.

A note on “black pad”: This process defect was a hot topic for a few years. That time has passed. The fabricators worked out the right amount of phosphorus in the nickel to prevent the defect that was more than a cosmetic issue. That concern was laid to rest.

ENIPIG: not too hard, not too soft. Electroless nickel, immersion palladium, immersion gold adds palladium as a physical barrier between nickel and gold. That opens up the process. The main benefit to ENIPIG is the outer layer of gold is soft enough to be a good candidate for wire bonding, while still working well for soldering. The alternative for chip-on-board is a selective soft gold finish: the do-everything finish.

When selecting the correct finish, know the constraints. While ENIPIG has an upcharge, it’s not as expensive as soft gold or hard gold when used in combination with medium gold. Note medium hardness is geared for solderability, while hard gold creates a more durable contact surface for “gold finger” edge connectors. To meet the specification for HDMI, the gold fingers must withstand 10,000 insertion/extraction cycles.

OSP: a minimalist approach. Organic solderability protectant is a very thin coating consumed by the reflow process. In the factory, we had to be aware of the date codes on boards with OSP. You don’t want old boards with this coating.

During design, when reaching back to padstack definitions, the designer must coordinate something extra when using OSP. We had to include a paste stencil opening on our test points when the boards had OSP, or the test points would end up with bare copper. The exposed copper will tarnish over time. None of the other finishes have this requirement.

An IPC specification for OSP (IPC-4555) is on the horizon. Per a report on this publication’s website in August 2020, “The goal is to develop performance specifications for high-temperature OSPs, defined as capable of withstanding up to two IR reflows in conjunction with tin-silver-copper (SAC) or tin-bismuth (SnBi) alloys at a peak temperature of 245°-250°C and showing the same wetting balance results at three reflows as zero, with a maximum 20% drop.”

This is good news since OSP is well-suited to mass production runs. The micro-thin coating does not hinder solderability. The cost is low, along with the shelf-life. Organic solderability protectant has been around for quite some time with proprietary processes, so it will be beneficial to have a performance standard across the board. 

JOHN BURKHERT JR. is a career PCB designer experienced in military, telecom, consumer hardware and, lately, the automotive industry. Originally, he was an RF specialist but is compelled to flip the bit now and then to fill the need for high-speed digital design. He enjoys playing bass and racing bikes when he's not writing about or performing PCB layout. His column is produced by Cadence Design Systems and runs monthly.

Shake, rattle and roll: Your devices often experience it all.

The stark choices of organisms are to adapt, move or die. Our electronics sometimes tough it out so we can do our jobs or simply have a good romp on our favorite ride. No matter the purpose, extreme weather puts an electrical system to the test.

Whether the element is sand, saltwater, sunshine or perhaps a lack of thereof, many dangers age a system prematurely. Most faults caused by the environment are single-component failures. Okay, a part failed. Why? What is the root cause, and what can we do to prevent it from becoming part of a larger trend? Answering that two-part question is the gist of reliability engineering.

What broke is not always evident. Cosmetic damage or a burn scar may point the way if you’re lucky. In most cases, diagnosis is not that easy. Check connectors first, while the board-level investigation usually centers around the FETs that bring power to the device that is out of spec or failing altogether. Somewhere in there a tiny junction has burned up. The repair and return unit or perhaps field service technicians are a good source of reliability anecdotes.

Shock and vibration over time will make anything rattle itself to pieces. We can run into unexpected issues with resonant frequencies. Remember the footage of the Tacoma Narrows Bridge. “Galloping Gertie” came down, as the roadway itself was wind-tossed into 30' waves. The same thing happens on a smaller scale and at higher frequencies all around us. Something will begin to rattle in the wind until it breaks off.

Spread out components to relieve heat buildup. What separates high-reliability PCB footprints from standard ones? You’ll see the difference in the size of the solder pads. Expect more room for the toe fillet. This often increases the personal space around the component, while providing additional metal-to-air interface area for convective heat dissipation. The additional spacing created by the extra metal may not seem like much, but on aggregate has been shown to reduce junction temperatures.

Derating for system robustness. The other thing that separates high-reliability footprints is simple. Stuff them with components that are better than good enough. Twice as good is a high bar, and a good place to start when it comes to derating components. If a 50V cap is sufficient, go for the 100V version.

Chunky hardware with closer spacing isn’t just for the steampunk effect. Plan a few mounting holes in the middle of the board, rather than just the corners. You’ve seen a heat map. The hot spot isn’t on the edges. As a practical matter, a gratuitous hole here or there could be a bargaining chip as the board evolves into something more crowded than originally planned. You know what they say about plans.

FIGURE 1. While this overnight accumulation looks tame to some, moisture is an archenemy of electronics (and other metal objects).

FIGURE 2. The car suffers in the midday sun, and I come along and demand it envelop me in a cocoon of frigid air. Like it or not, that’s hard on the equipment.

Commercial- versus industrial-grade components. It was easy to distinguish the TTL packages of yesteryear. The high-reliability units had a device number “54,” rather than the “74” used on commercial versions (FIGURE 3). LS stands for low-power Schottky, which predates the even lower-power CMOS architecture. This example is a stand-in for the universe of components that follow this technology path.

FIGURE 3. This hex inverter circuit plays out on different footprints, starting with DIP packages, and then SOIC became the surface mount version for the plastic package. The underlying silicon underwent several iterations, and the high-reliability versions are on their own package outlines. (Source: Netsonic)

Operating ambient temperature range and package comparison:

54 = -55°C min., 125°C max. Packages: CDIP, LCCC, CFP
74 = 0°C min., 70°C max. Packages: PDIP, SOIC

Ceramic packages withstand a greater range of temperatures than plastic ones. No surprise high-reliability packages are not always the smallest available. It’s a paradigm that carries through connectors down to passives. Get those commits early and nurture them so the part pipeline is there when you need it. Mil-spec parts are an upgrade whether the board is Class 3 or Class II commercial, so it’s about cost and availability.

Use adhesives and conformal coatings to prevent unintentional disassembly. For everything to stay put, a shaker table will be part of your life. These instruments of mechanical terror are specially designed to shake other smaller things to the point of failure. You can only imagine how overbuilt a shaker table must be to outlast whatever is bolted down on its base plate.

When the dust settles, the weakest link(s) will be revealed, and additional actions can be taken. During the preproduction trials on the Pixel laptop, we had a connector that would not stay put after the 3' drop test. We hope you never give your laptop a 3' drop onto concrete, but if you do, a little bracket holds the USB connector in place.

Riding around on the roof of a car is another challenge you should never have to face. Putting a Lidar detector up there, on the other hand, can be loads of fun (FIGURE 4). Simultaneous location and mapping (with the somewhat unfortunate acronym SLAM) require an immense amount of processing while jostling around through rain and sleet. The connectors, in particular, are well overbuilt, especially when you’re looking for a place to put that ethernet port. Nonetheless, a bead of glue around the base is an insurance policy. Post-assembly coatings make rework next to impossible but also protect the devices from failure, making it a good idea for space-bound projects.

FIGURE 4. A car roof is a good place to be out in the elements. Any outdoor location will do, while motion will amplify the effects.

Use heavier copper to give the boards some backbone. Not sure if anyone besides those in the PCB industry use copper weight as the significant variable to determine its thickness, but here we are. Take 1 oz. of copper, keeping in mind it is very malleable, and shape it into a 1' square of even thickness. That’s 1 oz. copper and typically about as much as would be used for the outer layers, while the innerlayers typically get half that.

Both inner- and outer layers can be plated up. One result of this is an increase in the minimum trace width and spacing geometry. The thicker the copper, the coarser the line-to-line pitch becomes. At the extreme, an entire base plate of copper with no circuit pattern can be incorporated into a board. That could be a solid copper bottom layer or as a central metal core. For a local effect, a so-called coin can be embedded as an integral heat sink.

Shock mount electronics inside a cage within a cage. Flight cases offer a standard 19" equipment rack-mount isolated from a secondary outer case that ensures the contents are not subjected to sudden g-forces from being loaded and transported. Something is better than nothing when it comes to bolstering the unit against the expected use-case.

Depending on where you want to go and what you want to do, your electronics must be hardened against failure. We are often the cause. Who hasn’t dropped their phone? The reliability lab focuses on finding root causes of failure. Take whatever measures are necessary and prudent for the perils the gear is likely to face.

Sometimes, reparability will suffer for the effort of making it bulletproof. The motivation is to reduce or eliminate repairs in the first place. Fail fast and go to mass production with the most solid product you can put out there. Your customers will then put it to the test so you can continue the cycle of continuous improvement.

JOHN BURKHERT JR. is a career PCB designer experienced in military, telecom, consumer hardware and, lately, the automotive industry. Originally, he was an RF specialist but is compelled to flip the bit now and then to fill the need for high-speed digital design. He enjoys playing bass and racing bikes when he's not writing about or performing PCB layout. His column is produced by Cadence Design Systems and runs monthly.

Getting all the parts and processes aimed in the same direction.

Printed circuit board technology never sleeps. At this very moment, engineering teams are working out ways to increase circuit density with finer-pitch devices. When it comes to placing these components on a PCB, the margin of error shrinks along with the pin pitch. Let’s look at how we can enable these parts on the assembly line.

The first step in mass production of a PCB assembly is preparing the board to take components. The boards may be baked in an oven prior to starting the assembly process. Although they are packed in sealed containers with a little bag of desiccant, the sponge-like dielectric materials still absorb water one molecule at a time. Prebaking releases the steam that could interfere with reflow soldering.

Ideally, all parts on a board will use the same type of technology and will be roughly the same class of components in terms of pin-pitch and other physical aspects (FIGURE 1). Tall and heavy components plus small and light ones are not a good mix. Tall ones create so-called shadows where the surrounding area doesn’t get as hot during soldering.

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