Features Articles

As our alternative energy column comes to a close, the author contemplates the past and the future.

Read more ...

Boundary scan and embedded test will need to make up for ICT gaps.

Read more ...

Smaller component technologies on the horizon, and the mix of parts to be placed, will present severe demands on accurate solder paste deposition.

Read more ...

Stencil use leads to lower tension, and eventually misalignment. Is there a solution?

Anyone with even a modicum of understanding about the printing process knows that stencil (or screen) tension is integral to print integrity. While the amount of tension is important, what’s even more critical is that the proper tension is evenly distributed across the stencil. There is also some evidence that points to higher tension being more effective than lower tension, particularly for today’s finer-pitched devices and especially when there is an extremely high density of apertures. Take a stencil for one of today’s mobile phone printed circuit boards (PCB), for example. These stencils tend to have more holes than stencil, so tension is critical.

On average, tensions between 30 and 35 Newton are a good starting point for a properly tensioned stencil. If the tension changes over time – either from process use or post-process cleaning – the printing integrity will be affected. When apertures are filled, the board and the stencil come together like a sandwich. If the tension in any part of the stencil has diminished, as the print stroke begins, the stencil image moves and gets pushed away with the direction of the squeegee. As the apertures are being filled, there will be misalignment as the print stroke progresses and it becomes increasingly difficult to keep the print process in control.

When the board is released from the stencil, a well-tensioned stencil will produce a very controlled release. If the stencil has become baggy and less tense, the stencil will follow the board down with the table so, instead of a complete clean separation, some parts of the stencil will separate before others. In the high-density areas of the board – where there are many, many 0.4mm CSPs and hundreds of 0201s or 01005s – there is a large volume of solder paste that wants to stick on the apertures. This condition will tend to pull the stencil down, resulting in an uncontrolled release.

Traditionally, mesh mounted stencils have been the stencil architecture employed most frequently in electronics assembly. When using a metal mesh (as opposed to a polyester mesh) from which the stencil is suspended, extremely high tensions can be initially created. However, mesh mounted stencils tend to relax and lose tension as they are used and cleaned. Consider that the entire stencil is placed into the cleaning system that uses temperature and chemistry to clean off solder residues. Then, the stencil is dried with hot air. Cleaning and drying are inherently bad for the adhesive materials used to manufacture mesh mount stencils. This process results in varying coefficients of thermal expansion, which cannot only weaken the elasticity of the stencil and mesh, but can also cause the stencil image to shift. When processing fine-pitch devices, this is highly problematic.

So, what’s the solution? The best option would be to clean the foil only and preserve the integrity of the tension. This is precisely the idea behind many of the market’s frameless stencil tensioning systems. With these stencils, the foil is separate from the frame, which has many advantages. While some of these systems faced early challenges (operator injuries from sharp edges, for example), these obstacles have been overcome, and the popularity of frameless stencils has grown in recent years. There are many benefits to frameless stencil technology, including storage space savings, sustainability, lower costs over the long term and, most important, no loss of tension over time. The stencil foils are cleaned once removed from the frame, so there are no concerns about mesh or adhesive impacts. When placed into the frame, the foil is tensioned to the same level each time and, because there is no mesh to contend with, there is no loss of tension – even in high-volume manufacturing environments. In comparison, mesh mounted stencils used in high-volume processes need to be replaced an average of every two to four weeks.

In the past, frameless stencils provided tensions of 30 to 35 Newton, which was fine for standard SMT (0.5mm pitch and above) but not for today’s miniaturized devices. If using these systems for fine-pitch processes, a frameless stencil that can provide a tension of 40 Newton or greater is required for a robust process. Anyone considering a frameless stencil system needs to bear this in mind during the selection process.

The new challenges of miniaturization dictate now more than ever that stencil tension is consistent. Tighter pitches combined with thinner stencils and high-density apertures make stencil tension control and uniformity an increasingly critical parameter. In this case, tension is indeed a good thing.

Clive Ashmore is global applied process engineering manager at DEK International (dek.com); cashmore@dek.com. His column appears bimonthly.

How clean is “clean?” And how can one tell?

What are the required cleanliness levels of printed circuit boards, and how will contamination ultimately affect the long-term reliability of electronic assemblies? This is one of the hot topics in electronics manufacturing. So, how clean is clean? A critical factor to consider is what level of product reliability is required. Answering this question is complex and requires detailed examination.

Numerous methodologies for assessing PCB cleanliness are common practice within the industry. They range from rapid tests that detect only certain types of contamination to more complex methods that are subject to the latest IPC testing standards. All are useful tools for qualitative and quantitative assessments. Which to use is a matter of preference and, of course, the process quality standards and product reliability requirements set forth by the end-customer or OEM.

Visual inspections are performed in accordance with IPC-A-610E, Acceptability of Electronic Assemblies, to detect the presence of visible surface and under-component residues. The results qualitatively assess the presence of residues. Other commercially available and easy-to-use methods include flux, resin, copper, phosphor, halide and ink tests. The ink test is applied to the solder mask and visually qualifies surface cleanliness through the determination of surface energy, while the other tests provide evidence of specific types of residues via color reaction, either on the substrate itself or by using a test strip.

More complex methods include ionic contamination, ion chromatography and surface insulation resistance (SIR), to mention just a few. These tests vary in complexity and depth of analysis, and each is performed in accordance with IPC test methods.

Briefly, ionic contamination testing is a measure of average ionic contamination on the board surface and is generally used to determine if PCBs conform to the requirements of a process performance specification. Ion chromatography measures the levels of anionic and cationic contamination present on a board surface. It is an interesting analytical method that determines the pass/fail limits of each ionic species based not on IPC standards but rather as established on a case-by-case basis. In the absence of industry standards for specific ion levels, the end-customer often defines the allowable limits based on prior experience and the product’s end-use environment. SIR testing helps show the impact of flux residues on the electrical reliability of a device and is often conducted using industry standards. This test is designed to expose a processed or unprocessed printed wiring substrate to elevated temperatures and humidity while applying an electrical potential to determine the propensity for electromigration.

In practice, one or more of these tests are used by manufacturers as a part of their internal quality procedures or as part of a qualification process. Field experience has shown that often manufacturers find existing contract requirements have changed or different demands must be met to earn new business. A thorough understanding of one’s manufacturing process and available test analytics may not be enough to meet the required process demands or test requirements for a new product specification. In these cases, consulting with process experts can be beneficial.

In a case we were involved with, a full-service EMS provider was using ionic contamination testing as part of its quality process for numerous products and consistently exceeding the cleanliness specification of less than 10µg/in2. To secure additional business with a new customer the firm was required to pass an SIR test. Following current practices regarding its cleaning processes, it found that it was unable to pass. The failure was traced to residual flux, particularly underneath components. Thus, even though its core products were manufactured to specification using ionic contamination as a measurement, the qualified cleaning process failed to clean the assemblies to pass the SIR test. Once the failure’s origin had been identified, we helped assess the cleaning process and optimize all parameters so that the EMS firm was able to pass the SIR test and secure the new business. Following the final qualification, the customer incorporated the cleaning process improvements for all products, thereby enhancing the overall product quality for all its customers.

In various other cases, a variety of test techniques were used to evaluate a current cleaning process and assist processors in meeting their cleanliness requirements. Utilizing the types of rapid test techniques mentioned earlier can assist in identifying the presence of residues and the potential for failure and steer one toward an appropriate, more sophisticated test technique.

Other analytical test methods include electrochemical migration resistance and surface organic contamination testing, each performed in accordance with IPC standards. Electrochemical migration testing provides a means to determine the propensity for surface electrochemical migration. It can be used to assess soldering materials and/or processes. Surface organic contamination testing, also referred to as nonionic analysis, is used to determine if organic, nonionic contaminants are present on a bare printed wiring board and completed assembly surfaces.

How clean is clean, and how can you tell? It just depends. Having an understanding of the test techniques available, and the purpose of each, as well as the product reliability requirements, will point you in the right direction.

Richard Burke is national sales manager at Zestron USA (zestronusa.com); richard.burke@zestronusa.com.

When higher preheat temps and longer contact time don’t improve hole fill, what’s next?

Problem

  • Wave soldering process cannot achieve topside fillets on thermally challenging assembly.
  • Operators manually touch up 100% of solder joints on specific components.

PCB Description

  • 3"x12" power management PCB is 150 mils thick with heavy copper planes throughout and ENIG final finish.
  • It is densely populated with SMT components on both sides, and contains large PTH rectifiers and electrolytic capacitors.

Process and Equipment

  • The process uses SAC 305 solder and a popular, no-clean VOC-free flux designed for Pb-free wave soldering. Local environmental regulations mandate use of VOC-free flux formulations.
  • A selective solder pallet that holds two PCB assemblies shields the SMT components and adds additional thermal mass during soldering (Figure 1).
  • The PCB is preheated to a topside temperature of 100°-108°C and has 8.3 sec. of wave contact at a conveyor speed of 1.25 ft./min. (Figure 2).
  • The wave solder machine is an Electrovert Electra outfitted with a spray fluxer, three bottomside forced air preheaters, three topside Calrod preheaters, and nitrogen-inerted chip and smooth waves.




Diagnosis

  • Process engineers have tried improving hole fill by re-profiling to increase preheat temperatures and/or contact time, but cannot get better results. In many cases, the results get worse as more heat or wave contact is added. The process shows classic symptoms of flux burnout.

Improvement strategy

  • Switch to a flux that has better thermal endurance and methodically step up the heat in the process, observing changes in PCB temperature and solderability.

Results

Run 1: Change flux; maintain same process parameters and evaluate results.

  • No change in topside hole fill
  • Indicates flux activity or loading is not a factor

Run 2: Begin increasing preheat temperatures with small step of 30°F per preheat zone.

  • Marginal change in topside temperature
  • No change in topside hole fill, indicating need for more heat


Run 3: Increase preheat setting by additional 50°F per zone.

  • Topside PCB temperature up to 110°C
  • Some improvement in hole fill, but not quite yet acceptable

Run 4: Increase preheat settings by another 50°F per zone. Increase flux loading by changing valve factor parameter from 50% to 70%.

  • Topside PCB temperature up to 120°C
  • Topside temp >100°C for 2 min. to raise PCB core temperature
  • Considerable improvement in topside fill, most joints are acceptable



New process:

  • The new process maintains the same belt speed of 1.25 ft./min., but now achieves a topside temperature of 120°C and 11.5 sec. of total contact time (Figure 4).
  • The VOC-free no-clean flux leaves no visible or palpable residue and provides high post-soldering electrical reliability.
  • Quality and throughput are improved; costs and bottlenecks associated with manual touchup are reduced.

Karl Seelig is vice president of technology at AIM Solder; kseelig@aimsolder.com. Carlos Tafoya is technical applications manager at AIM.

What is Flux Burnout?

Flux burnout occurs in wave soldering when the flux’s activators get spent in the preheat portion of the process, before the circuit board reaches the solder wave. It can happen to no-clean and water-washable fluxes, and can present big problems on thermally massive PCB assemblies.

When heated, flux activators begin removing existing oxides from solderable surfaces, and continue removing new ones that form during the heating process. They should remain active throughout the soldering cycle to facilitate wetting, but have a finite lifespan. If the activators are fully expended during the preheat cycle, new oxides build up and hinder joint formation.

PCB assemblies with high thermal mass challenges – design elements like thick copper planes, bulky components or poor thermal relief on ground ties – need extended preheat cycles to warm them to soldering temperature and extended wave contact times to let solder wick up the holes. It is not uncommon for thermally challenging assemblies to experience flux burnout, especially with the slower conveyor speeds of Pb-free wave soldering processes.

Diagnosing flux burnout. Try this simple test: slow the wave solder machine’s conveyor speed and examine hole fill.

  • If slowing the conveyor improved hole fill, the flux was still active. The increased preheat and contact time resulted in better hole fill.
  • If slowing the conveyor did not improve hole fill, the flux was spent. The flux stopped cleaning the oxides before soldering was completed.

Most wave soldering fluxes are designed to maintain activity and reliability across a wide process window, from fast and cool profiles to slow and hot ones. When high thermal mass PCBs demand extreme time-temperature exposure, typical flux activators may not survive. Specialized activators with enhanced thermal endurance are needed to ensure good solder wetting, acceptable hole fill and reliable mechanical performance.

Page 70 of 77