Smaller component technologies on the horizon, and the mix of parts to be placed, will present severe demands on accurate solder paste deposition.

The printing process spans across many different electronics market sectors from automotive to lighting to industrial to communications, with each application having its unique requirements and priorities. The automotive market, for example, demands extreme reliability, whereas manufacturing priorities for the communications market might be more dictated by speed and high throughput. But when it comes to which sector is actually driving technology advances, mobile communications is arguably the leader. In fact, experience shows that it is the developers and manufacturers of mobile communications devices – today’s smartphones, tablets, ultrabooks and more – that are the early adopters of leading-edge technology.

Mobile communications are defined by small form-factors, exceptionally high functionality, 24/7 connectivity and long-term reliability. That’s what consumers want. To address consumer demand, assemblers require advanced systems and technologies to cope with extreme miniaturization, all while maintaining high yields. Readers will be familiar with the statistic that’s commonly cited: printing is one of the critical processes in printed circuit board assembly, as a reported 60% of defects originate at the printing phase. In short, getting the print right is essential. And, getting it right 99.9% of the time becomes increasingly difficult as assemblies become smaller and densities much tighter. The printing process has seen significant advances, but it must continue to transform to meet near-term and longer-term manufacturing realities.

So, what will printing look like for the electronics assembly industry in the near future and the far future? There’s no doubt that the small will get smaller, which will have dramatic implications for the printing process.

From Past to Present

Looking back just 15 years, the average mobile phone PCB measured 130 x 40mm and typically contained some 200 to 300 components. The finest-pitch device used was likely a 0.5mm QFP. Today, popular smart phones have shrunk by approximately 50%, while component counts have doubled – and even tripled – depending on functionality. Many assemblies are now double-sided to accommodate the increased complexity (Figure 1). This all makes for extremely high-density, very fine-pitch assemblies, requiring exceptionally accurate and capable printing technology.

While 0.4mm CSPs once seemed far off, they are now considered mainstream technology for the mobile communications sector and are on the bill of materials (BoM) for just about every modern handheld product. The printing technology capable of coping with such fine-pitch components has existed for years, but only over the past few years have 0.4mm CSPs been incorporated into high-volume production, and 01005 resistors and capacitors even more recently. The industry has now reached the point that many predicted would be the ceiling in terms of current printing capability. Has printing technology really reached its limit?

The Near Future

Indeed, what most would call standard printing tools are certainly at the far edge of capability for 0.4mm CSPs and 01005s. Soon, however, the industry will face even smaller assemblies, the consequence of which is smaller components, finer pitches, increasing component densities, a higher mix of components, and thinner and more flexible substrates. Miniaturization has many implications, not the least of which is its driving force in advancing printing technology and guiding next-generation process development (Figure 2).

To understand the industry reality in the next two to three years (the near future), one only need reference IPC’s 2013 Technology Roadmap¹ for a fairly accurate picture of tomorrow’s requirements. Figure 3 illustrates advancing CSP component pitches and the projections for the near term. Realistically, the widespread adoption of the 0.3mm CSP format will happen over the next three years. This fact will require some not-so-standard printing tools, many of which already exist.

Although there are many important elements and outcomes of the print process, excellent transfer efficiency at high speed is the Holy Grail. Ensuring that proper volumes of material are centered on the pad in increasingly smaller dimensions has driven the most recent printing technology advances capable of supporting 0.3mm CSP deposition. Printing small isn’t the biggest challenge; it’s printing small volumes alongside large volumes that presents increasingly higher hurdles. To streamline the process and provide very high throughput rates, printing both small and large deposits in a single stroke with a single thickness stencil is the ideal scenario. Area ratio (the ratio between the aperture open area and the aperture wall surface area) fundamentally dictates the transfer efficiency of a printing process. Historically, engineers have worked with area ratios in excess of 0.6 to maintain a successful process. However, in recent years, aided by improvements in material sets, process engineers have pushed the process to ratios of 0.5 to accommodate leading-edge components. For the future, this basic rule will be pushed even further (Figure 4)!

To deliver robust transfer efficiency for heterogeneous assemblies (fine-pitch devices alongside standard SMT), novel tools and techniques will most certainly have to be employed. Let’s face it; achieving good transfer efficiency for 0.3mm CSPs and large connectors simply will not happen with standard print tools. To effectively print these smaller devices on increasingly higher density assemblies, SMT specialists will have to pull all of the toys out of the toy box, including:

• Active squeegee technologies that enable good solder paste transfer and increasingly smaller area ratios permit single-thickness stencil heterogeneous printing.
• Stencil nanocoatings to prevent paste from sticking to the bottom side of the stencil and encourage a more stable process through reduced cleaning frequency.
• More deliberate design of aperture shape (square vs. round) to encourage better transfer efficiency.
• And, potentially, the use of finer-particle solder pastes, such as Type 4.5 and above.

Some – perhaps all – of the above will be required to meet the printing requirements of the near future IPC Technology Roadmap projections. The good news is the tools exist.

But, there’s always that dreaded caveat. Not only must there be excellent transfer efficiency for ever-diminishing deposit sizes, but this must be repeatable in high volume. It’s not just miniaturization; it’s miniaturization and high-yield processing. To successfully achieve this combination, multiple elements of printing technology must align (Figure 5).

High-yield processing is all about producing more good boards per hour. While there is some overlap with miniaturization issues (i.e., getting the process right the first time and maintaining the process), high-yield printing has more to do with equipment capability than with process technologies. Not only will printing’s near future involve existing closed-loop feedback with solder paste inspection (SPI) to verify deposition offset (alignment) and optimize cleaning frequencies, but increasing print platform utilization will also be tantamount to improving greater throughput. For example, new machine technologies that deliver faster transport, alignment and cleaning, along with concurrent processing functions to minimize dead time, can reduce cycle time significantly.

Realistically, all these elements for the industry’s near future from a print capability perspective are achievable today.

The Far Future

Printing technologies to address the next three to four years of manufacturing requirements have existed since the mid 2000s, with print process innovation leaders consistently staying one step ahead of the industry curve. The author is optimistic that the same will hold true for the far future – defined here as five years out or more – but this will certainly require a major print paradigm shift.

According to the previously cited IPC Technology Roadmap, 0.25mm CSPs will be standard practice by the 2019. And, it’s also quite likely that metric 0201 capacitors (with dimensions of 250 x 125µm) will also be in the mix. In fact, engineering samples of the first metric 0201s will be available later this year. When what is now the far future arrives, the area ratio chart will need to be extended even further (Figure 4).

For the printing process, this has many consequences and will necessitate some unconventional approaches. Today, if one wanted to attempt printing
for such small components alongside larger SMT devices, a step stencil or a dual print process, plus all of the previously mentioned near future printing tools, would have to be leveraged for any chance at success. Given the past innovation, however, the goal of printing these fine features within heterogeneous assemblies with a single stencil may not be as farfetched as might be assumed. To be sure, stencil advance in one shape or form will be required.

One of the biggest challenges for printing technology’s far future, though, isn’t one that’s print-process-induced but is perhaps something deposition innovators can solve. Substrate – most often a PCB – quality (consistency of planarity and tolerances) is a hurdle even today. When the board tolerances are outside the stencil tolerances because of what the industry calls “board stretch,” misalignment is the result, and paste isn’t deposited precisely on the pad. With increasing assembly densities and decreasing pitches, board tolerances will have to be extremely tight for a successful print process. Perhaps producing boards as singles instead of panels could address the issue. In this case, each board would be individually aligned in a “virtual” panel technology prior to printing, which could potentially solve the tolerance and misalignment issue without adversely affecting throughput. PCB manufacturers have this singulation capability today; it’s the surface mount assembly market that’s driven panelization for mass production. A virtual panel approach might integrate the best of both worlds: individually manufactured boards but multi-board, panelized assembly processing. It is clear, however, that PCB quality must somehow improve if the industry is going to move into the far future with any level of certainty. Without it, the printing process may hit the proverbial wall.

What else might printing technology look like in the far future? Advances in SPI capability may be extended. Today, we use SPI to provide feedback for alignment and stencil cleaning optimization. In the future, print platforms will leverage SPI technology to extend this capability so as to enhance high-yield processing even more and reduce dependence on the operator. Printing machine intelligence will surely play a large part in progressing miniaturized, high-yield assembly processes.

The Crystal Ball Conclusion

None of us can positively know the future, but there are some relatively solid data about where the industry is headed in terms of consumer demands (Figure 6) and what that means for component sizes and assembly densities. Without question, the printing technology that exists today can accommodate the near-term needs. Staying a step ahead of long-term needs is now the driving force. Novel deposition methods, new stencil architectures, “virtual” panelized PCBs, faster and more highly-utilized print platforms, and increased application of SPI data – all of these possible scenarios will be the far future reality.

A total “lights out,” operator-free printing process is the ultimate goal for printing innovation. Whether the top deposition technologists can achieve this remains to be seen. But, then again, 10 years ago the industry was skeptical about printing 0.4mm CSPs in high volume and that 0.3mm CSPs would ever be in the realm of possibility, wasn’t it?

References

IPC, IPC International Technology Roadmap for Electronic Interconnections, March 2013.

Mark Whitmore is future technologies manager at DEK; mwhitmore@dek.com.

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