Abstract: The use of copper wire bonding in semiconductor packages has seen a steady evolution in recent years. The technology offers better performance and is more economical than traditional gold wire bonding, and Texas Instruments has played an instrumental role in developing copper wire bonding across the industry. With billions of units shipped, TI offers packaging solutions that deliver the performance, reliability, quality and cost advantages of copper. Copper wire bonding is a proven, standard solution across many of TI’s analog, embedded processing and wireless products, and it is gaining broad acceptance among customers. This white paper will explore the technology’s benefits and technical challenges faced in the ramp of copper wire bonding to high volume production.
May 23, 2012
By Jim Norton
In today’s electronics assembly environments, it important that workbenches and workstations meet the needs of the technician and the work being performed, along with the flexibility to change, add or reconfigure as processes change. Considering the wide variety of workbench choices available on the market, it can often be a daunting task to configure them to meet all of your requirements. There are two primary consideration that will effect each and every aspect of the decision: What is the work being done at each station, and how will it change in the future? The answers determine how each workbench or workstation is configured.
March 15, 2012
Author: Ivan Pokrovsky, New Russian Electronics, Business Industry Yearbook, 2008.
Abstract: Russia, which is characterized by smaller domestic contract surface mount assemblers, has been a difficult place for large multinational EMS companies to navigate. However, the nation's domestic electronics assembly industry is huge, with forecasts predicting a $14 billion industry in 2010, primarily (55%) for industrial or military end-markets.
By Abhay Maheshwari and Austin Lesea
Alpha particle emission in close proximity to the device circuitry is minimized by following Xilinx low alpha solder requirements on package substrate
pads. One flip-chip packaging vendor’s failure to comply with these requirements has resulted in contamination by high alpha solder causing possible
soft errors due to flipped device configuration bits. This white paper provides an overview on soldering material, describes the specific soldering problem,
and offers some solutions.
January 14, 2004
by Nolan Johnson, CAD/EDA manager, Sunstone Circuits
Design flows are a key contributor to the efficiency of the electronic product development cycle. But one needs to look a little deeper to realize that the prototype fabrication portion of the process is of critical importance in catching design errors early and effectively. It is the prototype hardware, after all, which verifies the original design intent embodied by the CAD file contents; the relationship is symbiotic.
By Dave Hemmelgarn, Application Engineer
The RapidView inspection system has further enhanced MPM screen printer high resolution capabilities with increased viewing area and improved resolution, sharpness and contrast over the previous generation of systems. The industry trend toward increased use of ultra-fine pitch devices has fed the demand for faster and more accurate vision systems. Paste coverage measurements for 2D inspection, as well as bridge detection on ultra-fine pitch devices, require a precise measurement system with high contrast images and the lowest possible geometric distortion.
Pin-gate molding structures are said to provide superior quality, reliability and performance, and can be less expensive than traditional corner gate molding. Amkor’s PGM process is designed with a JEDEC-compliant larger mold cap which has a number of benefits, including allowing the routing of active traces and vias within the mold cap dimensions, improving protection from solder mask cracking, and facilitating larger die sizes in the same form factor. In addition, Amkor’s PGM PBGA uses a package saw singulation process which produces a smoother edge on the package, reducing the potential for binding in the test socket and shipping tray, and thus delivering higher yields.
PGM is also a more cost-effective PBGA structure as it uses higher density substrates and smaller diameter wire than traditional corner gate molding. Gold wire diameter can be reduced by over 50% down to 0.5 millimeters. Copper wire diameters can also be reduced significantly. These capabilities also extend the usefulness of wirebonding to smaller silicon nodes. With PGM, wirebonding can now be used down to 28 nm.
The white paper describes the package, the process, reasons for the change and the current state of volume production.