White Papers

Introduction.

The objective of this White Paper is to provide users of the above products in the electronics industry a clear understanding of the different types of stencil cleaning
paper/fabrics that are currently available. Fine pitch applications are more the norm now and so the performance of stencil cleaning rolls is more critical than ever before. This White Paper will give solder paste stencil printing engineers and purchasing professionals an insight into the main products on the market, thereby enabling them to make informed decisions.

http://www.circuitsassembly.com/cms/whitePapers/SMT_Under_Stencil_Wiper_Rolls.pdf

Introduction: This document provides PCB designers with a set of guidelines for successful board mounting of Atmel surface mount packages. Package Land Pattern descriptions are depicted by the package family, and although each family is represented by a single body size and lead count, the individual land description apply to all packages within a particular family. Land Pattern descriptions were provided by IPC-7351 Calculator from the Mentor Graphics Corporation. These are only general guidelines that Atmel received from the IPC-7351 Calculator. The solder reflow guidelines are derived from IPC -9502. Atmel does not make direct recommendation for board design, nor does it take legal liability and responsibility for the information in this document. Please refer to the IPC website for more information regarding board design and processing.

http://www.atmel.com/images/atmel-8826-seeprom-pcb-mounting-guidelines-surface-mount-packages-applicationnote.pdf

"Water Vapor Principles"

By Gordon Davy, Ph.D.

Abstract: A discussion of relative vs. absolute humidity and diffusion into plastics.

Published March 2013

www.kondner.com/files/Vapor.pdf

 

This paper tries to explain the factors that influence the ability of surface mount solid Tantalum capacitors to withstand present industry standard reflow technologies, and explores the peak temperature trends of industry IR reflow systems.

http://www.avx.com/docs/techinfo/irreflow.pdf

 

"Sequential Lamination"

by Stanley L. Bentley, Divsys

Abstract: Sequential lamination is necessary when the design of the interconnect system has connections that are not required on all layers or that if made available on all layers would impact the system performance or create an unsolvable congestion in the design.

Published May 2012

"Copper Foil Weight vs. Thickness"

by Stanley L. Bentley, Divsys


Abstract: The copper foil on the printed circuit board has two very confusing units of measure. These
units are frequently mixed and confused for one another.

Published November 2012

 

Joint Project for Mechanical Qualification of Next Generation High Density Package-on-Package (PoP) with Through Mold Via Technology

Abstract:
This paper will summarize joint work between ST Microelectronics, Amkor Technology and Nokia; to qualify Amkor’s through mold via (TMV™) bottom package technology for next generation high density PoP applications. The 12 x 12mm daisy chain test vehicle reported in this joint work includes a thin flip chip die in a fully molded bottom package with 516 bottom BGAs at 0.4mm pitch and 168 top solderable through mold vias at 0.5mm pitch. This paper will report the package level (moisture resistance, temperature cycling) and board level (temperature cycle, drop) qualification data against IC and handheld application requirements.

Additional data for package warpage control and board level reliability for larger PoP applications using TMV technology will be included beyond what was reported at ECTC 1, SMTA International 2 during 2008 and IMAPS Device Packaging 3 in March 2009, based on a 14 x 14mm daisy chain test vehicle with 620 bottom BGAs at 0.4mm pitch and 200 top vias at 0.5mm pitch. Additional data on the TMV technology will be provided including: maximum die to package size design benefits for wirebond, stacked and flip chip die, coplanarity and package warpage measured by shadow moiré across lead free SMT reflow profiles. JEDEC standardization work for next generation PoP applications will be provided for mechanical and high density electrical interface requirements driven by low power double data rate 2 memory (LP DDR2), in single and dual channel architectures which require 0.5 and 0.4mm pitch interfaces respectively. 4

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