Package on Package (PoP) Stacking and Board Level Reliability, Results of Joint Industry Study

ABSTRACT / SCOPE OF WORK

This paper presents the results of a joint - three way study between Amkor Technology, Panasonic Factory Solutions and Spansion in the area of package on package (PoP) board level reliability (BLR). [BLR is also referred to as second level or solder joint reliability within the industry]. While PoP is experiencing exponential growth in hand held portable electronics applications, as reported by iSuppli [1] and others, to date PoP BLR data has been customer specific and not available for industry publication. Significant company internal and industry data exists to help optimize designs for BLR performance in 0.5mm pitch, Pb free fine pitch BGA (FBGA) or chip scale packages (CSP). In addition new work has emerged in 0.4mm pitch CSP as reported by Scanlan, Syed, Sethuraman, et al [2]. However, industry data specific to the reliability of the top to bottom PoP - BGA interface has been critical to designers in planning for new PoP applications or configurations. In addition, data was needed to validate whether current best practices for Pb free reliability performance of bottom 0.5mm pitch BGA to mother board interface still applies in PoP stacked structures.

The goals of this collaborative study were to:
· Compare popular Pb free ball alloys and BGA substrate pad finishes to determine, which solder joint and BGA pad finish structures show the best BLR cost / performance balance for the BGA interfaces.
· Establish collaborative PoP supply-chain relationships in order to generate applicable BLR data and make it broadly available to the industry.
· Ensure that PoP BLR data generated is comprehensive – based on the high volume design and manufacturability considerations for top, bottom packages and final PWB assembly.

This joint work is part of an ongoing project Amkor has planned to cover multiple package sizes, and stacking interface structures in support of aggressive PoP roadmaps. This paper is the first in a series of planned data releases to help facilitate PoP advancements, infrastructure development and industry standardization. The scope of this paper is to cover the already popular 14 x 14mm PoP package size that provides a 152 pin stacked interface which supports a high level of flexibility in the memory architecture for multimedia requirements.

This paper will summarize:
· The structure and reliability monitoring benefits of a three net PoP daisy chain design.
· Process flow, conditions and benefits with the single pass reflow SMT stacking process applied in the PoP stacking build.
· BLR test conditions and report reliability results measured.
· Concludes with suggestions for optimum BGA pad surface finish and Pb free solder ball material selection.
· Indicate areas planned for study in future PoP projects.