Package on Package (PoP) Stacking and Board Level Reliability, Results of Joint Industry Study Print E-mail
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Written by Moody Dreiza, Lee Smith, Gene Dunn, Niranjan Vijayaragavan and Jeremy Werner   
Tuesday, 23 October 2012 15:33

Package on Package (PoP) Stacking and Board Level Reliability, Results of Joint Industry Study

Authors: Moody Dreiza, Lee Smith, Gene Dunn, Niranjan Vijayaragavan and Jeremy Werner

Abstract: This paper presents the results of a joint three-way study between Amkor Technology, Panasonic Factory Solutions and Spansion in the area of package on package (PoP) board level reliability (BLR). (BLR is also referred to as second level or solder joint reliability within the industry.) While PoP is experiencing exponential growth in handheld portable electronics applications, as reported by iSuppli and others, to date PoP BLR data has been customer specific and not available for industry publication. Significant company internal and industry data exists to help optimize designs for BLR performance in 0.5mm pitch, Pb free fine pitch BGA (FBGA) or chip scale packages (CSP). In addition new work has emerged in 0.4mm pitch CSP as reported by Scanlan, Syed, Sethuraman, et al. However, industry data specific to the reliability of the top to bottom PoP-BGA interface has been critical to designers in planning for new PoP applications or configurations. In addition, data was needed to validate whether current best practices for Pb-free reliability performance of bottom 0.5mm pitch BGA to mother board interface still applies in PoP stacked structures.

Published: March 23, 2006

 

 

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