Packaging Players Face High Stakes Print E-mail

OSATs are facing off with foundries over next-gen packages.


Two poker games occurred at the IMAPS Global Business Council and International Device Packaging Conference held in Ft. McDowell, AZ,  in early March. One was a game of Texas Hold’em for attendees; the other had much bigger stakes.

Time was, companies were vertically integrated, and large semiconductor companies established and maintained assembly operations to produce packages. While a few companies, including IBM, Intel, Samsung, Texas Instruments and others, maintain strategic assembly operations, many companies shifted to the “asset light” model, and the era of the fabless semiconductor emerged. The industry is potentially entering a new stage with the move to 2.5D (chips mounted on silicon interposers) and 3D with through silicon vias (TSVs). Will the fabless model still produce the high margins of the past? Is the industry moving back to its past with a new vertical integration infrastructure?

TSMC has announced that it plans to cut the outsource service assembly and test (OSAT) suppliers out of the assembly of silicon interposers it produces – and eventually 3D TSV assembly. The growing concern over that infrastructure model was evident at one panel session. The panel included representatives from TSMC, GlobalFoundries, UMC, Qualcomm, Hynix, Amkor and ASE. The argument is that the thin, delicate wafers cannot be shipped from the foundry to the OSAT for assembly without potential damage, and that responsibility for a defective finished product would be difficult to determine. TSMC describes the 3D TSV process as extremely complex, and says it should handle an assembly process with equal complexity, including everything from substrate design to dicing the micro-bumped wafers and assembling the finished stack into the package. TSMC already provides bumping and wafer level packaging services, but the new proposal is a step into territory typically reserved for the OSATs. This play would cut OSATs out of the high-value segment of the market. (Of course, TSMC will leave assembly of the lower value package types to OSATs.) With IBM, and now Intel, offering foundry services, as well as having internal assembly operations, the stakes are high in the game to dominate the market. Samsung, a vertically integrated OEM that also offers foundry services, is maintaining a low profile and not showing its hand. Other foundry service providers such as GlobalFoundries have announced they will not provide assembly services and will work in conjunction with OSAT partners. UMC will make silicon interposers and supply them for use by OSATs.  The silver lining, as ASE notes, may be if the foundries get into the assembly business, margins for packaging – and assembly may increase.

Commercialization of 2.5D and 3D technology will be enabled by continued process improvements. Papers and panel sessions at the conference highlighted areas in the 3D TSV process that would benefit from new developments. The materials panel highlighted many new developments in underfills, dielectrics and materials for wafer bond/debond. The panel  indicated materials for the bond/debond process used in wafer thinning for the 3D TSV process are an area that could use the most improvement. Equipment makers EV Group and Suss Microtec described new system developments. Much progress has been made by individual
companies and consortia to improve the debonding process.

While technical issues still need to be resolved, supply chain and business issues are of increasing concern. With supply chain disruptions such as the earthquake and tsunami in Japan and flooding in Thailand in 2011, some companies are not happy with the model that does not permit second sources for interposers and assembly.
The complexity of silicon interposers and 3D TSV assembly is not being debated. The difficulty of dicing thin wafers fabricated with ultra low-k dielectrics, and bonding the die with micro bumps using new materials and processes, is not in question. Stresses during the assembly process must be carefully managed to prevent delamination of the silicon itself. Selecting materials, developing the assembly process, and executing the turnkey operation to produce a finished package with high yield will be challenging, and it is not clear to everyone which group has all the necessary skills. TSMC has clearly demonstrated successful completion of various 3D TSV process steps. However, the first product samples of die assembly on interposers were a joint effort involving die design by Xilinx, fabricated by TSMC, with Amkor providing assembly on an organic substrate manufactured by Ibiden.

Which strategy will provide the best results and move these new technologies into high-volume manufacturing is an open question. With all players holding their cards close to their vests, the industry is moving into a new era with ramifications for the future infrastructure.

[Sidebar] What’s a Silicon Interposer with TSVs?

A silicon interposer acts as a transposer between the silicon die and package substrate. Communication between the die are possible by routing signals down through the interposer and up to the next chip. The advantages of silicon substrates result from the combination of the silicon material properties and multichip packaging, including:

  • High wiring density due to the very flat substrate.
  • TCE matched to the silicon die.
  • Excellent electrical and thermal performance.
  • Lower laminate substrate cost due to reduced wiring density.
  • Lower cost of active devices due to partitioning large die with minimal effect on performance.
  • Lower cost of active devices due to smaller flip-chip bump pitch.
  • Lower power requirements than equivalent single-chip packages due to multiple chips combined on one substrate.
  • Possibility of integrating passives into the substrate.

E. Jan Vardaman is president of TechSearch International (; This e-mail address is being protected from spambots. You need JavaScript enabled to view it . Her column appears bimonthly.



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