Packaging

“New Packaging and Interconnect Technologies for Ultra Thin Chips”
Authors: Christine Kallmayer, Rolf Aschenbrenner, Julian Haberland and Herbert Reichl; This e-mail address is being protected from spambots. You need JavaScript enabled to view it .
Abstract: This paper shows different approaches to use ultrathin chips for the realization of new packages with high density and improved performance. For several years, technologies have been developed for embedding chips in circuit boards to achieve 3-D packages using conventional PCB manufacturing processes. Ultrathin chips are suited to be integrated in rigid boards, as well as on and in multilayer flexible substrates. The use of interposers prior to embedding can facilitate ultra-fine-pitch component embedding. An example of a complex RFID-based product enabled by the integration of ultrathin dies is shown. (SMTA Pan Pac Symposium, January 2009)

Solder Joint Reliability

“Mechanical Failures in Pb-Free Processing: Evaluating the Effect of Pad Crater Defects on Process Strain Limits for BGA Devices”
Authors: John McMahon and Brian Gray; This e-mail address is being protected from spambots. You need JavaScript enabled to view it .
Abstract: Increased temperatures associated with Pb-free processes have produced significant challenges for PWB laminates. Newly developed laminates have different curing processes, are commonly filled with ceramic particles or micro-clays, and can have higher Tg values. These changes, aimed at improving the materials resistance to thermal excursions and maintaining electrical integrity through primary attach and rework operations, also have had the effect of producing harder resin systems with lower fracture toughness. Industry guidelines for mechanical stress limits were developed for materials processed using eutectic SnPb solders. A series of design and material implementations have gained wide acceptance to address mechanical failures at the corners of area array packages. Current accepted levels of process strain were established when the dominant and limiting failure mode was interfacial fracture (IFF) in complex intermetallic compound (IMC) layers at the solder/package interface. Changes in packaging processes, conversion to Pb-free solders and the subsequent compensation by laminate suppliers have produced significant shifts in failure mode occurrence, and the “pad-crater” failure mode has become far more common than IFF. By conducting a testing program that focuses on materials and geometries consistent with high-complexity “Enterprise Computing and Telecomm” electronics assemblies, and evaluating the results against the current industry guidelines, it is possible to determine whether the dominance of the pad-crater defect mode will require revision of process strain guidelines. Test methods, test results, failure analysis and likely mitigation techniques are discussed. (SMTA Pan Pac Symposium, January 2009)

“Corrosion Driven Whisker Growth in SAC305”
Authors: Keith Sweatman, Junya Masuda, Takashi Nozu, Masuo Koshi, and Tetsuro Nishimura; This e-mail address is being protected from spambots. You need JavaScript enabled to view it .
Abstract: Corrosion has been identified as one source of the compressive stress that drives whisker growth in high tin Pb-free solders. Here, the authors report a study directed at identifying the relationship between the extent of corrosion and the concomitant whisker growth. Printed circuit coupons with an OSP finish were soldered with SAC 305 using wave, reflow and hand soldering methods with no-clean fluxes typical of current commercial practice. These coupons were exposed to conditions of 40°C/95%RH, 60°C/90%RH and 85°C/85%RH for up to 5000 hr. As well as recording the location of whiskers, their density, and length as a function of time, the extent of corrosion was measured on cross-sections through the solder. The highest incidence and fastest growth rate occurred on test pieces exposed to 85°C/85% RH. The incidence and growth rate of whiskers was found to vary with the soldering method. (SMTA Pan Pac Symposium, January 2009)

Substrate Technology

“Emerging Substrate Technologies for Packaging”
Author: Henry H. Utsunomiya; This e-mail address is being protected from spambots. You need JavaScript enabled to view it .
Abstract: This presentation outlines the market dynamics driving the development of advanced substrates in today’s industry landscape. Technological advancements have shifted from PCs to mobile applications like cellphones, MP3 players, etc. An overview of the technology revolution of substrates and their corresponding packages are discussed in terms of technology supply chain matching: assembly technology, substrate technology and system technology. Advanced substrate technology roadmaps of leading Japanese suppliers are reviewed. The evolution of buildup substrates, which have standardized under the direction of CPU and FPGA manufacturers, are explained. The two technological directions of substrates for advanced electronic packages – miniaturization and functional integration – are mapped and explained in terms of “More Moore” and “More than Moore,” respectively. Fine-pitch wiring on substrates can be combined with embedded active and passive devices and has been proven. Examples and illustrations of advanced substrate applications in servers, handhelds, and high-end servers and communications equipment are reviewed. (SMTA Pan Pac Symposium, January 2009)

This column provides abstracts from recent industry conferences and company white papers. With the amount of information increasing, our goal is to provide an added opportunity for readers to keep abreast of technology and business trends.