Methods for Printing Cell Conductors Print E-mail
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Written by Darren Brown   
Thursday, 01 October 2009 00:00
  

The two primary ways need more repeatable accuracy.

In the July issue of Circuits Assembly, in presenting the direction taken by the 2009 iNEMI Roadmap chapter on Photovoltaics, Alain Harrus and Jim Handy underscore that the principal barrier to widespread adoption of PV technology is its cost compared to the energy it generates. They go on to point out that just over half of an installed PV panel’s cost is in its conversion technology: the cells’ capacity to capture and convert solar energy. It is here innovation is most likely to occur.

Indeed, in recent years, as sunlight has become increasingly attractive as a sustainable alternative energy source, the PV industry has made significant inroads in improved efficiencies, to the point that today, a good solar cell is capable of harvesting up to 18% of the solar energy that hits it. Clearly, there is room for improvement, as Harrus and Handy point out, but to achieve this, we can no longer push the boundaries on existing technologies, as their capabilities have been stretched to their limits. This means the PV industry must develop revolutionary new ways to improve efficiencies.

The industry can work in a number of directions to achieve this: One, as Harrus and Hardy outline, lies in improving the cell’s conversion capacity – the efficacy with which it transforms captured sunlight into electricity. Another perhaps more fundamental approach is to ensure the light capturing parts of the cell receive as much sunlight as possible.

Last month, I mentioned the PV industry is investing heavily in reducing the width of the silver conductor grid screen-printed onto the front side of the cell, and that effectively shadows the precious light-capturing real estate below. With current feature widths at 100 to 120 µm, this shadow effect has been reduced as much as it can be using existing PV processes. Finer line work, although it may not sound overly complicated to anyone active in electronics production, requires a step change in technique and approach. This is because, to maintain their conducting capacity, finer lines must stand higher. This is not as simple as it sounds; the finer the line, the lower it stands – thanks to print paste rheology and the physical properties of screen printing stencils.

One solution is to print the conductors twice over, effectively doubling their height. This is achieved using Print on Print (PoP) technology, and enables us to print features down to 50 to 60 µm wide without compromising their precious conductive capacity. It is clear that here repeatable accuracy is key – as we know well from our experience with this procedure for the semiconductor and biomedical sectors. This is because this degree of resolution calls for excellent wall definition, and therefore, a perfect gasket must be formed between the substrate and the underside of the print screen, calling for alignment accuracies to within an exacting 10 µm.

PoP capability also comes into its own in the selective etching cell structuring technique, whereby an etchant is screen-printed onto the cell’s surface in a grid pattern identical to that of the conductor grid. Upon heat activation in an oven, the etchant removes the cell’s non-reflective top layer and exposes the silicon underneath, so that in the subsequent print pass, the silver grid enters into direct contact with the cell’s active energy-transforming layer.

In a similar vein, the selective emitter process aims to increase efficiencies by printing extra n-type dopant in a pattern mirroring that of the collection grid. The fact that the two patterns must be aligned to within 10 to 12 µm is complicated by the fact that the dopant is invisible. This precludes the use of conventional vision systems, so two small fiducials, to which the two deposition processes must be precisely aligned, are typically etched on the edge of the cell.

With growing emphasis on these new PoP processes, it is clear that, if it is not already, repeatable accuracy is soon to become key for solar cell and module manufacturers, especially if we consider that the PV marketplace is far from mature, and that as panel prices come down, we can expect massive increases in production volumes. Current industry throughput rates, which at 1200 wafers per hour are already fast for those of us used to electronics manufacturing standards, are expected to increase in the very near future to twice or even three times that rate. This will put even more pressure on us to ensure our processes are accurate, and repeatably, reliably so. Sophisticated, powerful metrics such as the Process Capability Index (Cpk), long used by the semiconductor and board assembly sectors, will soon become critical for the PV industry too, as manufacturers strive to maximize end-of-line yields, reliability, and bottom-line performance. 

Darren Brown is business development manager, alternative energies at DEK International (dek.com); This e-mail address is being protected from spambots. You need JavaScript enabled to view it . This column runs periodically.

Last Updated on Friday, 04 December 2009 13:39
 

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