3-D IC Bonding Print E-mail
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Written by Chris Sanders   
Thursday, 03 September 2009 18:19

Supply-chain roles are changing, with EMS firms expected to take a bigger chip-packaging role. 

As semiconductor packaging sees higher density interconnects and smaller scaling, it presents both a challenge and an opportunity for traditional electronics assembly providers. Previously, semiconductor wafers (produced by an OEM or a foundry) were shipped to an outsourced semiconductor assembly and test (OSAT) provider, where they were diced and packaged. Then the packaged devices were sent to an EMS facility to be soldered on a PCB or other substrate that would eventually become part of a finished system. Under this supply-chain flow, the tasks of the foundry, OSAT provider and EMS facility were completely separate, with each step in the semiconductor supply chain delivering the next level of assembly service from wafer to finished product. However, advances in semiconductor design technology, along with increased market pressure for higher density devices, yield improvements and cost reductions at all levels of the supply chain, have led the industry to rethink these traditional roles.

With conventional scaling of semiconductor line widths reaching its practical and economic limits, many chip designers have embraced some form of 3-D IC integration to achieve goals of higher-density devices. These new 3-D ICs carry implications for semiconductor packaging houses, as well as traditional EMS companies, providing an opportunity to expand their services.

3-D IC basics. To determine how 3-D IC technology would impact the various steps in the semiconductor supply chain, it is necessary to examine the different methods used to implement 3-D IC integration, and how they would impact current packaging and assembly processes.
Most 3-D IC designs begin with wafers developed using established high-volume processes to take advantage of foundries’ economies-of-scale. Many designs incorporate embedded metal through-silicon vias (TSVs), which form the interconnection between chip layers once the processed wafers are thinned to expose them, and then they are bonded to form the 3-D stack. If the 3-D integration is designed primarily to provide additional density, then the ICs being bonded can be of similar composition.

However, different semiconductor materials can be used to add functionality to a base IC layer, such as RF or analog functions that complement the overall system performance. Because different semiconductor materials require different – and often mutually exclusive – processing steps, some form of 3-D integration is the only method to produce such a hybrid chip without resorting to external packaging, which adds cost, complexity and bulk to the overall device.

The wafers (or die) used for 3-D IC integration are bonded using one of several methods: adhesives, heat and pressure, or direct oxide bonding (Figure 1). Each of these bonding technologies has specific limitations that can affect the overall yield, cost and interconnect density of the finished devices. Thus, the bonding technology has a direct impact on the ability of a semiconductor packaging and assembly provider to deliver 3-D IC integration services.

Fig 1

Adhesives. Adhesives are a common method for bonding semiconductor die or wafers. However, most adhesive materials cannot survive significant downstream wafer processes that require prolonged periods of elevated temperatures or pressures, so the resulting bond between the wafers does not exhibit the high level of mechanical robustness required for many portable electronic devices. Because of these process limitations, IC stacking is often limited to two layers. In addition, adhesive technology does not typically provide for interconnect, thus limiting the scalability of adhesive-based bonding schemes.

Copper-thermal compression. Another common method for ensuring a strong mechanical and electrical bond between wafers is metal-to-metal bonding, typically with copper as the bonding metal. In this process, wafers are aligned and then subjected to high (350° to 400°C) temperatures, while undergoing high pressure in multiple specialized chambers. The downsides are the high temperature has a negative impact on the CMOS; and the pressure needed affects the alignment accuracy and yields, and therefore, the scalability to smaller and smaller pitches is limited. Also, the time required in the specialized (read: expensive) processing chambers (up to 2 hrs. per wafer) dramatically impacts throughput (and hence, processing and tool ownership costs).

 

Fig 2

Direct oxide bonding. With direct oxide bonding, wafers to be joined are processed with embedded TSVs or tungsten plugs, which are exposed through wafer thinning. A layer of silicon oxide, combined with a bonding metal (such as nickel), enables the wafers to form a covalent bond at room temperature strong enough to hold the wafers together during downstream processing, forming a robust and reliable metal-to-metal interconnect bond. This technology can be used to build multiple layers of ICs with alignment tolerances of less than 1 µm, as tools for this purpose evolve, thereby providing advanced scalability.

The primary advantages of direct oxide bonding for semiconductor packaging and assembly providers are that it can be accomplished with minimal capital equipment expense (standard wafer pick-and-place and alignment tools, batch wafer heating processes); that it provides for high-yield, high throughput processing of multiple IC layers with high-density interconnections, and that it delivers the lowest overall costs for integrating 3-D ICs.
There are several specific processes for direct oxide bonding and chip interconnection, some patented.

We expect the role of semiconductor packaging and assembly firms to expand to include some form of 3-D IC integration. Those companies able to take advantage of the latest wafer and die bonding technology will become the suppliers of choice for leading manufacturers of portable electronic devices. 

Chris Sanders is director of business development at Ziptronix (ziptronix.com); This e-mail address is being protected from spambots. You need JavaScript enabled to view it .

Last Updated on Wednesday, 09 September 2009 18:43
 

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