Improving QFN Reliability Print E-mail
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Written by Joseph G. Ameen and Gilson V. Geralde   
Tuesday, 30 September 2008 19:00

The proper solder volume makes a dramatic difference.

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Small QFN packages (sometimes referred to as a micro leadframe package, or MLP) present processing challenges. The requirements for grounding the package bottom and making reliable connections to I/Os on the periphery on this same plane can be difficult. If too much solder is applied to the ground plane, the part will float, resulting in poor connections to the I/Os (Figure 1). If too little is applied, insufficient grounding will result.

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In addition, according to IPC standards, toe fillets are not required.1 This can severely limit the connection area. The toe surfaces are created when parts are diced from a lead frame. The lead frame thickness creates the toe (Figure 2). Because this surface is unprotected copper and usually oxidized, it is difficult to wet with solder.

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To improve device reliability, the proper amount of solder is needed to ground the bottom and simultaneously create a toe fillet. Several manufacturers and the literature2,3 offer suggestions for the ground area. This article focuses on the toe fillet and bottom connection, which create a kind of two-pronged connector, providing electrical continuity from both points.

Toe Fillet Influences

The first factor is the solder paste itself. Select a paste based on established criteria. For example, select a paste with the appropriate type (solder ball size) and one that does not slump within the process window (Figure 3).

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Profile the reflow oven in accordance with the QFN supplier’s recommendation. In this example, a paste supplier recommended a maximum of 230°C and an ideal temperature below 220°C. We set the oven around the 220°C maximized limit (Figure 4).

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Follow stencil guidelines so the pad-pulling tension to the retention wall tension ratio of the stencil is at least 0.6, and preferably higher. Based on a typical QFN’s pad sizes, the calculation indicates a 0.004"-0.005" stencil thickness works best.

Inspect the board pads that will receive solder paste. Ensure the solder mask is aligned with the I/O pads and the opening in the mask is not excessively large. This will eliminate wicking of solder over and down the pads’ sides (Figure 5).

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Solder mask misalignment or oversizing also could create I/O pads of varying lengths (Figure 6), making it difficult to control solder volume for even toe wetting. The goal is a uniform surface area that will accept a uniform solder volume. A good board supplier can help obtain the desired results (Figure 7). When the solder paste, reflow and board quality are controlled, it is possible to achieve nearly 100% filleting on the toes, while maintaining a good ground connection.

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Our internal inspection criteria are shown in Figure 8. A fillet that climbs the toe at least 50%, is not a thin coating on the toe, and is not excessive in volume (i.e., does not intrude into the space between adjacent I/Os) is considered an acceptable joint.

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Figure 9 shows a solder fillet inspection sheet prior to internal quality control, taking measures for all the aforementioned factors. Figure 10 shows the inspection sheet following QC. The white areas of the table are unacceptable fillets; the yellow areas are acceptable fillets. Fillet yields increased from 85.2% to better than 99.7%. Occasionally, 100% good fillets are achieved. Figure 11 shows typical results.

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By controlling the solder paste, reflow and board quality, it is possible to achieve toe fillets with a QFN, which should translate into better device reliability. Testing of QFNs with fillets that pass these criteria were subjected to 1000 hr. of burn-in at 70°C, followed by 600 thermoshock cycles between -40° and +85°C with no failures and no degradation in electrical performance. Results were achieved with SnPb solders, but the same principles should improve parts soldered with Pb-free solders.

Acknowledgments
The authors wish to acknowledge Ed Konopka for his useful review and proofreading of this paper.

References

  1. IPC-A-610D, Acceptability of Electronic Assemblies, February 2005.
  2. Carsem application note, “Comprehensive Users Guide,” April 2002.
  3. Duane Benson, “How to Succeed the First Time with Ultra-Small QFN Packages,” Microwave Engineering Online, Oct. 31, 2007.

Joseph G. Ameen is manufacturing process engineer and Gilson V. Geralde is in drafting at Herley-CTI Inc. (herley-cti.com); This e-mail address is being protected from spambots. You need JavaScript enabled to view it .

 

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