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Written by Dr. Charvaka Duvvury and Dr. Harald Gossner   
Monday, 31 March 2008 19:00

Proposed new ESD qualification requirements for HBM and MM.

The ESD qualification methods for ICs have a history of requiring performance to human-body-model (HBM) levels of 2kV, and in some cases 200V for machine model (MM). In recent years, CDM has come into focus, but specific requirements are unclear, other than 500V is a good benchmark value. The Industry Council has performed new investigations on ESD Target Levels to establish more realistic levels for HBM and MM.

The work was begun following observations that, for the past 10 years, numerous IC product qualifications encountered substantial bottlenecks because of ESD requirements. At the same time, it has become evident no field returns have been attributed purely to ESD damage, even for products shipped at less than the HBM or MM requirements. Simultaneously, rapid advances in silicon technologies, stemming from demand for higher performance circuits, are found to create increasingly restrictive component-level IC pin protection designs incompatible with the IO functions.

As a result of these effects, ESD qualifications started involving an exponential cost curve related to silicon respins to achieve the required levels at every advanced technology node, and eventually circuit degradation at the latest silicon nodes. (This is in addition to factors such as customer delays and extraordinary resources regularly spent by IC suppliers.)

To investigate the reality of ESD requirements, the Council launched a thorough investigation with detailed studies by the individual experts. Work was also done to note improvements implemented in ESD-protected areas with basic ESD control methods during the past 10 years. Billions of units shipped during the past five years at lower ESD levels were tracked to study the rate of returns. The following are highlights of this cooperative work:

  • Basic ESD controls typically practiced at production and assembly areas limit the static voltages generated to less than 500V.

  • Shipped devices (ICs and discretes) between 500V and 2000V HBM show ESD/EOS related failure rates at <1 DPM after tracking more than 20 billion units with several hundred different designs from different suppliers.

  • Failure rates of these devices are fully independent of the HBM level shipped.

  • The same trends are seen for both automotive and non-automotive products.

  • A vast majority of failure returns referred as ESD/EOS fails are attributed to EOS, and are unrelated to the HBM level.

  • HBM and MM levels track each other in a design dependent manner.

  • The inherent MM dependence on HBM indicates a worst-case MM level is 30V for HBM between 500V to 2000V.

  • While MM level is always available through HBM measurements, both 1kV HBM and 30V MM guarantee safe production within basic ESD-controlled areas.

  • Finally, the Council recommends adoption of 1kV HBM as the relevant new target requirement for IC qualification across all technologies to maintain the same product quality seen at suppliers, customers and product end-users.

Invariably the question arises whether the new recommended levels would have an impact on system-level ESD performance. First, as evidenced by the more than 20 billion unit data, no increase in system failures have been seen, even for products at 500V or 1kV HBM.

Second, when the IC is placed in a system board, unless it has direct interface pins, the system-level ESD test (which is very different from the component-level test) shows no impact. The protection for these types of interface pins is tested with the IEC method at the system level (IEC standard 61000-4-2), when the IC is mounted in the application board. Thus, the strategy of system protection design is different and requires a completely separate focus. But, the important point remains that a component-level ESD reduction has never shown sensitivity to system-level performance for products with no direct interface to the outside world.

The Council’s findings and recommendations are comprehensively documented in a white paper1 published in August 2007. The Council is diligently working to establish similar realistic requirements for charged device model (CDM).


  1. White Paper 1: A Case for Lowering Component Level HBM/MM ESD Specifications and Requirements,, August 2007.

Ed.: This was written on behalf of the Industry Council on ESD Target Levels, consisting of experts from ESD test equipment suppliers, major semiconductor corporations, OEMs and EMS.

Dr. Charvaka Duvvury is a Texas Instruments Fellow at Texas Instruments (; This e-mail address is being protected from spambots. You need JavaScript enabled to view it . Dr. Harald Gossner is manager, ESD division, at Infineon Technologies (


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