PALO ALTO, CA -- Agilent Technologies Inc. has introduced the Versatest Series Model V5500, a final test solution for multichip package devices (MCP) and discrete flash memory. The tester-per-site architecture and optional Programmable Interface Matrix are said to optimize single-insertion testing of MCPs with multiple memory types (Flash, DRAM and SRAM).

Has 16,384 pins per testhead, to fully utilize x320 handlers at up to 320 NAND devices in parallel. Enables parallel testing of high-pin-count NOR and MCPs at up to 256 devices in parallel.

Gayn Erickson, VP in the memory test division, said, "It radically reduces cost-of-test by allowing both high-parallel and single-insertion testing of MCPs. Especially with the Matrix, this new solution presents a key technology for enabling the industry's massive adoption of complex MCPs, which are crucial to the wide availability of 3G phones and other advanced consumer electronics applications."

Said to lower capital expense and test time through single-insertion test of all MCP memories. Each die is tested serially. Only a subset of the total I/O pins required to test the high-pin-count MCP is used to test each individual die.