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Written by Sandra Winkler   
Wednesday, 13 June 2012 09:54

San Diego, home to the world-famous San Diego Zoo and Wild Animal Park, also hosts the annual ECTC (Electronic Component Technology Conference) every three years. Attendance at this year’s ECTC was 1,230, up from 1,002 attendees the year prior.

This was the second-highest attendance since the inception of ECTC 62 years ago. A total of 359 attendees came to the 16 professional courses on May 29, and the conference boasted 81 exhibitors and 347 presentations. The program sessions ran from May 30 through June 1. With so many people in attendance, there was a high level of energy in the air, with attendees on the hunt for new information. There was plenty of that to be found.

Additional sessions at various times provided even more information beyond that of the main conference sessions.

A special session was held on Tuesday morning, titled Next-Generation Packaging and Integration: The Transformed Role of the Packaging Foundry. Chaired by Raj Pendse of STATS ChipPAC, speakers included Robert Lanzone of Amkor, Bill Chen of Advanced Semiconductor Engineering (ASE), Mike Ma of Siliconware Precision Industries, Steve Anderson of STATS ChipPAC, and Dan Tracy of SEMI. Capital expenditures are going up by an order of a magnitude with TSVs in the equation, making it difficult for OSATs to fund their own growth. The need for collaboration was brought up not only here, but in many other conference sessions as well. About 3% of the top OSATs’ revenue is designated for R&D, which is feeding new technologies and helping these companies find new ways to reduce costs.

2.5D is a hot topic, and is already in production in small quantities; bringing costs down will fuel the growth. TOs cost $35 in 1963 if the purchase price had not been artificially lowered (selling below cost), the industry would not have flourished as it did, when it did. The same will be true of other upcoming technologies—a lower cost will fuel purchasing power. The FOWLP, or fan-out wafer-level package, is opening up new possibilities of new markets. This technology can also enable a TSV stack; a dense interconnect silicon interposer will be needed for this.

In an effort to lower cost, many OSATs are moving to copper wire bonding, as the price of gold has become prohibitive. Because cost is such a strong underlying factor, the “high-end mentality” has to give way to trying the cheapest way first and building performance up from there. Producing something using the highest priced manufacturing technology makes it more difficult to reduce cost later.

The Tuesday night panel session, Power Electronics—A Booming Market, covered a technology hot primarily in Europe, for renewal energies, power supplies, e-mobility, LED systems, smart power electronics, and network control. New materials and technologies will be needed in this market. Aluminum ribbon, copper aluminum ribbon, or copper wire bonding will replace aluminum wire bonding, and silver sintering or diffusion soldering for die attach will improve device life. The demand for power electronics is very regional. The session was chaired by Rolf Ashenbrenner of Fraunhofer IZM and Ricky Lee of Hong Kong University of Science and Technology. Speakers included Dan Kinzer of Fairchild Semiconductor, Klaus-Dieter Lang of Fraunhofer IZM, Lionel Cadix of Yole Development, Ljubisa Stevanovic of GE Global Research, and Bernd Roemer of Infineon Technologies.

The Wednesday luncheon keynote speaker was Gregg Bartlett of GlobalFoundries. He mentioned the need for collaboration during design, something that previously didn’t occur. This will bring the best minds to the table at the outset. 2.5D and 3D require collaboration to make the whole fit seamlessly together. These technologies offer improved system-level performance and bandwidth with reduced latency and power requirements compared with competing technologies. 2.5D and 3D accommodate a smaller bump pitch. 2.5-D enables a “fission” of the CPU, GPU, and memory for high-bandwidth applications, integrating each chip individually into the whole so that each chip can have its own “needs” met, given that each involves different back-end processes. Silicon partitioning will occur with interposers, and increase with complexity, from FPGAs in 2011, memory cubes in 2013, and logic plus memory in 2013–2014 to, ultimately, wide-I/O memory on an application processor for more sophisticated heterogeneous stacking.

The Wednesday evening plenary session, Photonics, Expanding Markets, and Emerging Technologies, chaired by Christopher Bower of Semprius, covered LEDs, photonics integration on silicon, photonics packaging, and photonics to the processor chip. Speakers included Ashok Krishnamoorthy of Oracle, Jeff Perkins of Yole Development, Shen Liu of Huazhong University of Science and Technology, Alexander Fang of Aurrion, Timo Aalto of VTT Technical Research Centre of Finland, and Frank Libsch of IBM.

Packaging is 40% of the cost of an LED, or light-emitting diode. The cell phone was the first killer application for LEDs; general lighting—otherwise known as HB (high brightness)—will be the next big thing for the LED market. Currently the cost of an LED light bulb is anywhere from $15 to $40 with rebates, compared with less than $1 for an incandescent bulb, putting LEDs out of reach for most residential customers. There are no standards for HB LEDs, and thermal issues are huge. The cost of an HB LED needs to come down by a factor of 10, which will come about with a lower-cost packaging solution, such as wafer-level packaging.

The photonics industry in general does not have much in the way of standards. Photonics involve using light to carry the signal, rather than an electron. Photonics can be used in large-area data centers and on a single high-powered silicon chip. Uses abound in telecom, datacom, and computers. Because of the current high-cost manual processes to create photonic structures, efforts in recent years have focused on bringing costs down in a number of ways. In fiber-optic telecom uses, getting the package standardized, as in the IC world, has been up in the air for some time. Connecting the delicate fiber structures to a standardized package such as a butterfly package is difficult. The trick is to accomplish this without breaking the fiber-optic structures. Bringing photonics down to the computer level, either inter-chip or intra-chip, involves lowering the costs significantly by incorporating waveguides on silicon, a low-cost material. This is years away from actual production, and will require a killer application to justify spending the R&D costs to make it a reality. Germanium or some other material would have to be added to the mix, as silicon absorbs light, rather than reflects it, and the light cannot be absorbed if it is to continue carrying the signal down the line.

The final evening session on Thursday night was Advanced Coreless Package Substrate and Material Technologies. The co-chairs were Kishio Yokouchi of Fujitsu Interconnect Technologies and Venky Sundaram of Georgia Institute of Technology. Speakers included Yuji Nishitani of Sony, Tanaka Kuniyuki of Shinko Electric Industries, Takeshi Eriguchi of Asahi Glass, and Masateru Koide of Fujitsu Advanced Technologies.

Advantages of coreless substrates are several. Wiring capabilities allow direct signaling; all layers can be used as a signal layer. High performance comes from the lowest self-inductance and the highest mutual inductance. A coreless substrate is likely the widest bandwidth substrate structure.

Assembly problems include a higher warpage factor than with a cored substrate. Reflow is more difficult at higher temperatures. A number of options were presented to overcome warpage issues, including:

· Use of a clamp during chip attach.

· Use of lower CTE insulator prepreg materials.

· Use of a stiffener.

· Lower temperature soldering.

The program sessions ran for three full days, with six parallel sessions running at all times. Thus the topics to choose among were copious, and included advanced packaging methods such as 2.5D/3D, advanced interconnect, wafer-level packaging, LEDs, substrates, optoelectronics, modeling and simulation, materials and processing, RF, applied reliability, and emerging technologies. There was something for just about everyone connected to components, packaging, and manufacturing technologies (CPMT) in this jungle of options.

Sandra Winkler is senior industry analyst, New Venture Research (newventureresearch.com), and IEEE/CPMT Luncheon program chair.

Last Updated on Thursday, 14 June 2012 10:58


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