3D Packaging Options Proliferate Print E-mail
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Written by E. Jan Vardaman   
Wednesday, 31 August 2011 13:42

TSV will go mainstream, but for now a host of other options persists.

Companies and research organizations continue the challenging engineering work to develop 3D through silicon via (TSV) packages. Many presentations at Semicon West in San Francisco last July highlighted both challenges and achievements. While 3D TSV packages are expected to attain volume production in the future, a plethora of 3D configurations that do not involve TSVs are shipping in high volume today.

PoP. Smartphones and tablets continue to show strong growth. IDC predicts smartphone shipments will grow from 472 million units in 2011 to 982 million by the end of 2015. Apple reported that it sold 20.3 million iPhones and record tablet sales of 9.25 million iPADs in its most recent quarter, an increase of 183% from last year. These products make use of the 3D package-on-package (PoP) configuration where the top package typically contains wire-bonded memory, and the bottom package contains logic such as a processor. Increasingly, the logic device in the bottom package is using flip chip, including copper pillar. More than 500 million PoPs are expected to ship this year.

Stacked-die CSPs. The main application for stacked-die CSPs remains mobile phones, but the packages are also found in MP3 players, digital cameras, and other consumer products. New applications for stacked die include power management, automotive applications, and MEMS applications. More than 4 billion stacked-die CSPs will ship in these applications in 2011. While many are two-die stacks, an increasing number contain many more. Flash memory stacks account for the highest die stack count, with 16-die stacks in volume production.

QFNs Go 3D. QFNs are another high-volume package, and now there are 3D versions shipping in volume production. Texas Instruments has developed a 3D package for power devices called PowerStack and has already shipped more than 30 million units. Advantages include improved performance, greater power efficiency and improved chip densities in power management devices.

PowerStack is a unique QFN solution made possible through MOSFET stacking and copper clip bonding. In this 3D package, TI’s NexFET power MOSFETs are stacked on a ground leadframe using two copper clips to connect the input and output voltage pins (Figure 1). Stacking MOSFETs this way reduces size as much as 50% over a side-by-side package configuration. The package leverages a ground potential exposed pad to provide significant thermal optimization, reducing temperatures by more than 30%. The package improves efficiency by two points, reducing power consumption nearly 20% (at 20A).



For many in the industry, the 3D Holy Grail is the heterogeneous stacking of die with TSVs. There is no question that 3D TSV will be adopted, but the timing for mass production (millions or even billions of units) depends on how its cost compares with that of existing technologies such as stacked-die CSPs, PoPs and now stacked QFNs. 3D TSV is moving from PowerPoint into real engineering. Its demand remains driven by performance needs, and many companies have documented its benefits. Design, thermal test, and infrastructure issues remain barriers to TSV adoption in some applications, although progress is being made.

E. Jan Vardaman is president of TechSearch International (techsearchinc.com); This e-mail address is being protected from spambots. You need JavaScript enabled to view it . Her column appears bimonthly.

Last Updated on Wednesday, 31 August 2011 13:59
 

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