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Wednesday, 31 August 2011 00:59

Component Architectures

“Dark Silicon and the End of Multicore Scaling”
Authors: Hadi Esmaeilzadeh, Emily Blem, Renée St. Amant, Karthikeyan Sankaralingam and Doug Burger; This e-mail address is being protected from spambots. You need JavaScript enabled to view it .
Abstract: Since 2005, processor designers have increased core counts to exploit Moore’s Law scaling, rather than focusing on single-core performance. The failure of Dennard scaling, to which the shift to multicore parts is partially a response, may soon limit multicore scaling, just as single-core scaling has been curtailed. This paper models multicore scaling limits by combining device scaling, single-core scaling, and multicore scaling to measure the speedup potential for a set of parallel workloads for the next five technology generations. For device scaling, the authors used both the ITRS projections and a set of more conservative device scaling parameters. To model single-core scaling, measurements were combined from over 150 processors to derive Pareto-optimal frontiers for area/performance and power/performance. Finally, to model multicore scaling, the authors built a detailed performance model of upper-bound performance and lowerbound core power. The multicore designs studied include single-threaded CPU-like and massively threaded GPU-like multicore chip organizations with symmetric, asymmetric, dynamic, and composed topologies. The study shows that regardless of chip organization and topology, multicore scaling is power limited to a degree not widely appreciated by the computing community. Even at 22nm (just one year from now), 21% of a fixed-size chip must be powered off, and at 8nm, this number grows to more than 50%. Through 2024, only 7.9X average speedup is possible across commonly used parallel workloads, leaving a nearly 24-fold gap from a target of doubled performance per generation. (International Symposium on Computer Architecture, June 2011; cs.wisc.edu/vertical/papers/2011/isca11-darksilicon.pdf)

Reliability

“Predictive Modeling to Prevent Thermal Stress Failures in Electronics and Photonics”
Author: Dr. Ephraim Suhir; This e-mail address is being protected from spambots. You need JavaScript enabled to view it .
Abstract: Thermal stress is the major reliability concern and main reason of the finite service life of electronic and photonic assemblies, packages, devices, and systems. Predictive models can be experimental or theoretical. Both types of models should be viewed as equally important and indispensable tools for designing a viable and reliable device, and for making it into a marketable and cost-effective product. Analytical (“mathematical”) modeling occupies a special place in the modeling effort. Although it is true that powerful and flexible computer programs enable one to obtain, within a reasonable time, a solution to almost any stress-strain-related problem, it is also true that a broad application of computers has by no means made analytical solutions unnecessary or even less important. Simple analytical relationships have invaluable advantages, because of the clarity and “compactness” of the obtained information and clear indication on the role of various factors affecting the given phenomenon or the behavior of the given system. Accelerated testing, and especially accelerated life (failure-oriented) testing (ALT), which is the major experimental approach aimed, first of all, at the understanding of the physics of failure, cannot do without simple and meaningful predictive models; it is on the basis of such models that one decides which parameter should be accelerated, how to process and interpret the experimental data, and how to bridge the gap between what one “sees” as a result of accelerated testing and what they will supposedly “get” under actual use conditions. (Chip Scale Review, July/August 2011)

Solder Materials

“The Use of Preforms and Paste to Minimize Solder Joint Voids under Large Area Surface Mount Components”
Authors: Ellen Tormey, Westin Bent, Karen Tellefsen, Rahul Raut and Paul Koep; This e-mail address is being protected from spambots. You need JavaScript enabled to view it .
Abstract: Results of design of experiments (including variables such as preform size/location, preform-to-paste volume ratio, pad/via design and reflow profile) to investigate the effect of preforms on voiding under large area components such as MLFs, fusion quads and D-paks are presented. Pb-free SAC 305 preforms and paste are used for this study. Initial results show on average approximately a 40% reduction in voids percentage for large area components with use of the preforms in paste approach for forming solder joints. (SMTA International, October 2011)

This column provides abstracts from recent industry conferences and company white papers. Our goal is to provide an added opportunity for readers to keep abreast of technology and business trends.

Last Updated on Wednesday, 31 August 2011 14:05
 

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