Why it is Necessary to Change the IC ESD Target Specification Levels Print E-mail
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Written by Dr. Charvaka Duvvury, Dr. Harald Gossner and Dr. Jeremy Smallwood   
Wednesday, 07 July 2010 16:21

After 20 “static” years, more realistic measures are needed.

In the late 1970s, with the advent of large-scale integration (LSI), ESD started to become a problem. Electronics manufacturing companies soon started to implement ESD control programs. At first, there was little information sharing and no ESD control standardization. Early standards focused on ESD risks from people and on ESD protective packaging. Standards for ESD control items, such as wrist straps, work surfaces and flooring followed as improvements to ESD control materials and equipment were made. In 1999, the ANSI/ESD S20.20-1999 standard for ESD process control was published. A third-party certification program was established to demonstrate compliance with the standard. Eight years later, updated versions of the ANSI/ESD S20.20-2007 and IEC 61340-5-1:2007 standards were published. Facilities compliant with these standards expect to be able to handle devices down to 100V for the Human Body Model (HBM) without significant problems. In this context, adding ESD protection to bring device ESD withstand to 2kV HBM seems to be a case of over-engineering.

In the early days, devices had relatively small numbers of pins and were assembled largely using manual processes in relatively uncontrolled ESD environments. The likelihood of large amplitude HBM ESD events occurring to pins was relatively high. Over time, the number of device pins has increased dramatically, as has the level of manufacturing automation. Many devices can only be assembled in automated manufacturing systems, and ESD control has greatly improved. The likelihood of large amplitude HBM ESD has significantly reduced in these manufacturing processes. However, the number of protection networks required, and chip area they occupy, has grown along with pin count. Device ESD susceptibility test time and difficulty has increased correspondingly. When devices fail to meet the targets, the price of redesign can mean months of delay to product introduction. The ESD targets are particularly difficult to meet on high performance (e.g., low leakage or high-speed) pins. ESD protection networks add capacitance and leakage paths. At 45 nm and 32 nm technology, 18 Gb/s cannot be met with 2kV ESD protection, but can be with 1kV or less.

The potential benefits of reduced ESD target levels are clear. These include savings in design time and effort, faster release of production devices, accelerated and easier improvements in device performance and reduced chip area occupied by ESD protection networks.

Since the mid 1980s, it has been industry practice to supply ICs with ESD protection, where possible, to meet 2kV HBM ESD. While IC suppliers make every effort to meet these established ESD target levels, customers tend to expect these same levels without exception for product qualification. There is really no concern from either side, as long as these de facto levels are met. However, many quality and product engineers observe, with increasing frequency, that the advanced IC products have been encountering product qualification delays at every advanced technology node. At the same time, numerous products have been shipped with ESD protection on some pins at lower levels (after agreement with customers) to achieve desired performance. Despite this, field return rates have not been observed to be different from the products shipped at, or exceeding, the normal target ESD levels. These observations clearly indicate the target ESD levels must be considerably higher than necessary. Even more important, it leads to the conclusion that these levels could be universally reduced with no outside impact, while allowing the design freedom necessary to meet the technology advances.

Consolidated studies. To investigate and establish the true nature of these initial observations, a consortium of ESD experts known as the Industry Council on ESD Target Levels was launched in 2006. This council mainly consists of IC suppliers, consultants, contract manufacturers, and OEMs. It conducted massive studies on the existing ESD control methods and their relation to field return rates of IC products shipped at different ESD levels. The main conclusion was that with the basic mandatory ESD control methods practiced at every production area, products shipped at 500V HBM design levels are just as safe as products shipped at 2kV HBM levels. This is a clear confirmation that the current 2kV HBM target is an over-specification and that reducing this to 1kV should not have any impact on the customer qualification requirements.

With the introduction of recommendations on more practical, but still safe ESD protection target levels, some customers naturally show concern that there could be hidden impact on the reliability of the whole system itself. That is, while product yields may be unaffected, systems using these components might start showing unexpected failures in operation due to reduced ESD immunity. First, this concern arises from a misconception that the HBM component ESD test method represents the stresses that happen in a system environment where ESD transients are actually remarkably different in nature. Second, the data gathered by the Industry Council did not show any evidence of increased return rates from customer applications at 500V compared to 2kV HBM rated parts. The second fact naturally follows from the arguments from the first. The third, and most important, point is that electronics systems in operation require special protection strategy independent of the component-level ESD protection. Component-level protection is driven solely by the need to prevent damage during handling in the production area. So, component-level protection changes should not warrant a concern for system-level protection, provided the proper system protection is designed and followed. These same arguments also apply for Electrical Overstress (EOS) failures, which are independent of component-level ESD protection. All of these observations have been fully documented in a white paper published by the Industry Council.1

Epilogue: Since publication of the recommended HBM target levels, the Industry Council also has conducted detailed studies of charged device model (CDM levels). As a complement to HBM, CDM represents metal to metal discharge from the package leads and is an important ESD specification. For CDM, the industry de facto standard has been 500V. However, rapid advances in silicon technologies, high-speed circuit designs and IC package advances are making it virtually impossible to meet this level for many of the large pin devices with high-speed serial link designs at the 45 and 32 nm nodes. Similar to HBM for human handling, production area CDM controls to prevent metal to metal discharges have progressed far enough to safely recommend lowering this target to 250V.2 Both HBM and CDM requirements have been documented as JEDEC white papers.

The time has come for ESD target levels to be changed for the sake of the industry. IC suppliers should always guarantee the recommended minimum ESD levels are achieved. Electronics system manufacturers should diligently follow ESD control methods, according to standards such as IEC 61340-5-1 and ANSI/ESD S20.20, to prevent ESD damage during component handling and assembly in production areas. A general appeal is made to IC customers to keep component ESD protection level requirements at a realistic perspective and adopt the recommended new ESD target levels.

The Industry Council intends to publish a new white paper on effective system-level protection. This is an important subject, but should not be tied to component ESD levels.

Without these common goals, IC technology will continue to run into roadblocks during ESD qualification. With a common approach and better communication, a balanced ESD strategy can be achieved. The most important initial step is to remove the barriers by recognizing that new ESD level changes are urgently needed.

1. JEP155, Recommended Target Levels for HBM/MM Qualification, esdtargets.blogspot.com.
2. JEP157, A Case for Lowering Component Level CDM ESD Specifications and Requirements, esdtargets.blogspot.com.

Dr. Charvaka Duvvury of Texas Instruments (ti.com) and Dr. Harald Gossner of Infineon Technologies (infineon.com) are co-chairs of the ESD Industry Council (esdtargets.blogspot.com); This e-mail address is being protected from spambots. You need JavaScript enabled to view it . Dr. Jeremy Smallwood is a consultant at Electrostatic Solutions Ltd. (static-sol.com).

Last Updated on Wednesday, 07 July 2010 19:01


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