The Inevitable Demise of SMT Print E-mail
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Written by Randall Sherman   
Tuesday, 11 May 2010 18:44

Printed electronics offer the best chance for a process revolution.

The printed circuit board process has been around since before the start of WWI and has only been improved upon since the conception of etched copper traces on a single-sided substrate. Significant improvements since include:

  • Etching both sides and interconnect with eyelets, realizing twice the interconnect capability.
  • Introduction of the plated through-hole, eliminating the eyelets.
  • Multiple layer (multilayer) construction, creating several etched inner cores, laminated with presses, then forming PTH interconnections.
  • SMOBC: Solder mask over bare copper, eliminating reflow of the SnPb, allowing smaller traces.
  • SMT (surface mount technology).

A multitude of packaging techniques: Buried vias, where innerlayers are interconnected with PTHs; BGAs; blind vias, where small holes are laser-formed for interconnections, etc.

All these refinements were evolutionary, as none eliminated the basic principles of chemical etching and metal finishing. Indeed, some other “improvements” have simply complicated the manufacturing process to the point where yields become a big factor. In many high-tech boards, it’s really hit-and-miss, sorting the good from the bad.

With printed electronic circuits (PEC), however, the product is reduced to four simple, repeatable steps. At every fourth step, the product can be tested and reworked, eliminating the huge scrap of the old methods. Removing complexity reduces the capital investment required by up to 80%, yet the process should be considered “green” because it eliminates the PTH. Thus, the end-product should prove much more reliable, as the interconnect is a solid metal plug instead of a thin layer of copper plating.

Applications range from the most “impossible” designs to their simplest print-only counterparts, starting from RFID to forming a circuit trace on a hypodermic needle probe. Sub-mil lines with equal spaces, and buried and blind via formation, can be accomplished with nothing more than a silkscreen press.

As packaging density increases, the potential for more reliable end-products increases, with bonuses for economic and environmental benefits. Therefore, PEC may very well become the next-generation interconnect packaging method of choice for a very large portion of electronics. Existing PCB manufacturers must get on board, lest a new startup overtake the interconnect market.

With the demise of captive PCB operations, board manufacturers that doubled as technology developers have diminished. These were the board makers that at one time pushed the PCB fabrication envelope by introducing new processes and increasing reliability. Not much remains of those players today, and those left are converters. This is sad because innovation isn’t coming from the board shops, but rather from (sometimes outlandish) customer requirements, with board shops in turn struggling to make the product. Innovations in printed electronics now involve product designers, not the layout guys, and the process is very simple.

Basic conductive inks now are available. These include a low resistance silver (4x resistance of copper) and an LPI (photoimageable dielectric), which have produced 0.001˝ with UV exposers and sub-mil lines should be possible with LDI equipment. Silver conductive ink for now will satisfy commercial needs, and we expect that R&D efforts worldwide at the university level, as well as commercial alliances, will eventually lead to a conductive nanoparticle copper ink.

Traditional PCB processes require many consumable products. For example, a drill bit might make 3,000 holes, so to build a common 25,000-hole PCB requires eight bits, at a rough cost of $16. Much chemistry is used and must be disposed of, such as dry film, excess copper and tin, plastic sheeting, release films, press pads, router bits, and so on.

By comparison, whatever is used in the PEC process remains on the board. While inks are more expensive than those used in the PCB process, the overall costs are less because a multitude of activity-based requirements are eliminated, not to mention the floor area and related costs (HVAC, lighting, etc.), power requirements to heat and cool the multiple processes, and on and on.

The PEC process is reworkable in every step, so there is no scrap. The old process banks on (the hope for) integrity of the inner traces, such as plated-hole formation, to be completely perfect until final testing is performed. In fact, a bad board is built alongside a good one, and that is a waste of money.

At the end-user level, board reliability could be improved because there is no weakness in solid metal via formation. PTH reliability, on the other hand, worsens as holes become smaller and metallization gets more difficult. With the advent of cooler solders and conductive adhesives, PEC stands to be a better product.

Is it 100% ready? Certain suppliers provide materials and process from which product can be made for evaluation purposes for the more complex assemblies. Other less-critical applications where the process can be applied abound.

Is this the beginning of the end for SMT? The answer is probably “yes,” although the timeline is undetermined.

Au.: My thanks to Mike DuBois of Caledon Controls for much of the content of this article.

Randall Sherman is president and CEO of New Venture Research Corp. (newventureresearch.com); This e-mail address is being protected from spambots. You need JavaScript enabled to view it

Last Updated on Wednesday, 12 May 2010 17:17
 

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