What’s Driving Electronics Packaging and Assembly Trends? Print E-mail
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Written by E. Jan Vardaman   
Monday, 30 April 2012 12:19

Multi-die configurations and a switch to copper wires are rampant, and supercomputers are why.

One of the main topics at conferences around the world is what’s the driver for electronics packaging for the next 10 years? The Joint Conference of the 12th International Conference on Electronics Packaging and IMAPS ALL Asia Conference that convened in Tokyo in late April was no exception.

With speakers from Japan, USA, Europe, China, India, Korea, Malaysia, Singapore and Taiwan providing insightful presentations, it was clear there are many new developments in packaging and assembly from the standpoint of processes, package designs, materials and assembly equipment.

The tablet and smartphone have replaced the PC as the volume driver for packaging and assembly. Smartphones accounted for 472 million units or almost 27% of the mobile phone market in 2011, and expectations are that it will continue to grow at double-digit rates. Smartphones typically contain more than 20 CSPs, including some of the most advanced packages, such as package-on-package (PoP) and multiple stacked-die packages. IDC reports that 68.7 million tablets were shipped in 2011, a number expected to increase to approximately 106 million in 2012. Tablets use many of the same packages found in smartphones. Future tablets and smartphones are expected to use 2.5D or 3D TSV technologies; the only question is when volume manufacturing will begin. The consensus is 2013 at the earliest for these applications.

New 3D packaging techniques, such as the multi-die DRAM package from Invensas, are available. Sony provided details of its chip-on-chip (CoC) process, used for years in its portable game machines.

While tablets and smartphones drive volumes, supercomputers, servers and network systems still drive many advances in packaging and assembly technology. Computers, network systems and telecommunications equipment remain major applications for high-pin-count BGAs. Server OEMs use both ceramic and laminate BGA packages. At ICEP, Fujitsu outlined its 55.5 x 55.5mm glass ceramic BGA with 2,408 I/Os for its supercomputer. While both IBM and Fujitsu continue to use glass ceramic substrates in packages for high-end systems, future substrates are likely to be organic. The challenge will be how to achieve cost targets with the organic substrates, as the need for finer feature sizes of less than 10µm increases. Yield enhancement will be the battle cry on production lines of the future.

Copper, copper, everywhere. From bumps to wires, the industry is migrating to copper, as summarized by Renesas. Many companies continue to shift packages from gold to copper wire bond to reduce cost. While some analog products, memory and stacked die configurations still use gold wire, many other device and package types are converting to copper wire bonding.

Copper pillars are on almost everyone’s flip-chip roadmap and will drive investment in bumping technology over the next few years. While one of the first flip-chip introductions at IBM used a copper ball, the recent high-volume adoption of copper pillar can be attributed to Intel. Intel selected copper pillar because it is a reduced Pb-content solution that offers better thermal performance, improved electrical conductivity, and resistance to creep and electromigration, compared with conventional solder. Additional advantages include lowering the bump’s critical dimension floor, and continued downward scaling of the passivation opening size. The copper pillar process also provides options for tighter silicon and package routing pitches that can lead to higher pin densities and reduced die sizes. The copper die bumps permit use of a simplified under bump metallization (UBM) since the diffusion barrier requirements of the UBM are no longer required. Today Intel uses copper pillar through its entire flip-chip production. Companies including Texas Instruments have adopted copper pillar for form factor, decreased bond pitch and cost reduction reasons. Copper pillar is also used in 2.5D packaging where the die are mounted on a silicon interposer, and planned for many 3D packaging solutions where active die will be stacked on top of each other.

Copper has become the material of choice for filling the through silicon vias (TSV) in interposers and stacked devices. While there are some exceptions where tungsten is used for the vias, most designs focus on the use of copper. Copper pumping is still mentioned as an issue with its use, but companies are increasingly citing ways to mitigate this problem.

New materials. Materials for underfills, mold compounds and die attach continue to be introduced. With the emphasis on improving yield of the thinning process in 3D TSV, materials for wafer bond and debond are being introduced. The need to understand interactions between materials in the various processes has become the “full employment act” for those with a materials science background.

From LEDs to 3D TSVs, getting the heat out remains a challenge, and many companies are developing new materials to improve thermal dissipation. New package designs are coming out.

With packaging and assembly accounting for an increasing portion of the value of the total device cost, emphasis on the backend is growing. New materials, processes and package designs will continue to emerge, driven by the volumes in phone and tablets and performance needs of high-end systems.

E. Jan Vardaman is president of TechSearch International (techsearchinc.com); This e-mail address is being protected from spambots. You need JavaScript enabled to view it . Her column appears bimonthly.

Last Updated on Monday, 30 April 2012 15:28


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