PoP Needs a Perfect Print Print E-mail
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Written by Clive Ashmore   
Friday, 30 March 2012 10:16



Misprint the first package and place the second, and it’s too late for rework.

You may be wondering just what printing has to do with the package-on-package process, as the actual process of package stacking doesn’t have a lot to do with printing requirements. But, in a recent conversation with a customer about our technology roadmaps and the synergy therein, the subject of PoP and the importance of printing integrity came up.

PoP is one of those technologies that has just sort of snuck in; we’ve talked about it almost on the periphery, but it’s here to stay and advancing quickly. In fact, next-generation PoP designs thinner and even more complex than their predecessors – through-mold via (TMV) PoP, for example – are being seen in production of certain devices. When discussing PoP with this particular customer, it was in the context of just how central the printing process is for the first-level interconnect, or the package to the substrate. When one considers the increasing cost of PoP with the addition of the second-level package, the integrity of the print of the first level component becomes more critical than ever. Alignment, paste volume and reliability all have to be spot on. If there are issues with the original interconnect, then huge amounts of money, time and effort have been wasted.

In my opinion, this is a critical moment in SMT. All of these architectural developments and innovations seem relatively simple as standalone technologies. Put a package on a substrate? No sweat. Put a package on a package? Not that difficult, really. But, when you start to add up all the requirements, the aggregate becomes extremely tricky and costly if you get it wrong. And, when you factor in decreasing dimensions, the complexity element goes way up. Right now, the prevailing pitch with PoP is 0.4mm, even as large as 0.5mm in many cases. The customer I referred to earlier, however, is already starting to see the requirement for 0.3mm pitch. It’s precisely the convergence of all of these factors – changing device architectures, vertical integration, miniaturization – that make the precision of the printing process all the more important.

What were once printing technology “nice to haves” are now “must haves” and nothing illuminates this fact more than PoP. Now let me climb onto my soapbox and give you my must haves: ensuring the solder paste is precisely where you need it; there is a sufficient amount of paste on the pad; there is no solder paste leeching between apertures and causing bridging; your process can manage increasingly challenging aspect ratios inherent with finer-pitches; if alignment starts to veer off course, it will be automatically corrected – all are essential requirements with PoP. If the first package is placed, the second package put on top, and it’s not until final test when you discover the first interconnect is wrong, it’s too late. The package can’t be reworked, so two packages are being scrapped – not just one. With PoP, bill of materials (BoM) costs rise exponentially and, therefore, the print process must leave no room for error.

Admittedly, PoP isn’t mainstream at the moment. Rest assured, integration of vertical device stacking is only going to increase, and the added value to the process will move right along with it. Fortunately, just as device architectures have advanced, so have printing technologies and materials. I have touched on several process-enhancing tools and techniques in the past, all of which are now coming home to roost with PoP. For example, new nano-stencil coatings help enable a crisp, clear print, even with finer-pitch dimensions. Inhibiting flux and solder paste from leeching out into the stencil web, nano-coatings have been proven to raise process stability and improve yield. Type half solder pastes incorporate a tighter particle size distribution, which allows for sufficient paste volume, even on finer feature assemblies. Squeegee technology that energizes solder paste can push past prevailing 0.6 area ratios to sub-0.4 ratios and deliver more robust transfer efficiency. And, if alignment starts to get out of whack or cleaning isn’t optimized, closed-loop printers can automatically adjust these conditions. These technologies, along with intuitive software, high-performance consumables, well-manufactured stencils and good, solid process control procedures, will go a long way toward delivering excellent yields for PoP processes.

As I said before, this is a critical juncture for SMT. Technology convergence and device development places even more importance on the printing process. Are you prepared for PoP?

Clive Ashmore is global applied process engineering manager at DEK International (dek.com); This e-mail address is being protected from spambots. You need JavaScript enabled to view it . His column appears bimonthly.

Last Updated on Friday, 30 March 2012 16:37
 

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