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Tuesday, 31 January 2012 17:32

Board Coplanarity

“PCB Dynamic Co-Planarity at Lead Free SMT Temperatures”

Authors: John Davignon, Ken Chiavone, Jiahui Pan, James Henzi, David Mendez and Ron Kulterman; This e-mail address is being protected from spambots. You need JavaScript enabled to view it .
Abstract: With the advent of larger packages and higher densities/pitch, industry has been concerned with the coplanarity of the substrate package and PCB motherboard. The iNEMI PCB Coplanarity Working Group generated a snapshot in time of the dynamic coplanarity of several PCB designs from four market sectors. This paper investigates trends in dynamic coplanarity between market sectors, board thickness and global versus local area of concern measurements. It addresses whether room temperature coplanarity measurements can predict coplanarity at Pb-free assembly temperatures. (Pan Pac Symposium, February 2012)

Die Stacking

“Near Term Solutions for 3D Packaging of High Performance DRAM”

Authors: Vern Solberg and Wael Zohni
Abstract: Stacking two or more memory die with perimeter located bond pads has been fairly successful, yet because the die elements will typically have the same physical outline, spacers are needed between layers to clear the wire-bond loop height. Additionally, overall finished package height can be critical for a number of applications. Even though the die elements can be made very thin, the accumulated elements within the stack can be excessive. High-performance DRAM die are especially difficult to stack, due to the center-positioned wire-bond sites. This factor has complicated the die-stacking process and because of the excessively long wire-bond interface, functional signal speed is significantly degraded. This paper explores positive and negative aspects of the package assembly variations noted above, comparing both performance attributes and physical limitations. The authors introduce an innovative, thin 3D package design and assembly process developed specifically for center-bond pad DRAM die. The methodology requires no special die-level process steps and utilizes the existing package assembly infrastructure. (International Wafer-Level Packaging Conference, October 2011)

Solder Joint Reliability

“Joint Properties of Au Stud Bumps Joined with Sn-3.5Ag Solder by Flip Chip Bonding”

Authors:
Young-Kyu Lee, Yong-Ho Ko, Sehoon Yoo and Chang-Woo Lee
Abstract: The effect of flip-chip bonding parameters
on the formation of intermetallic compounds (IMCs) between Au stud bumps and Sn-3.5Ag solder was investigated. Flip chip bonding was performed at 260°C and 300°C with bonding time of 5, 10, and 20 sec. AuSn, AuSn2, and AuSn4 IMCs were found at the interface of the joint, and (Au, Cu) 6Sn5 IMC was observed near copper pads in the joint. At a bonding temperature of 260°C, AuSn4 IMC obviously grew more over time than other Au-Sn IMCs. At a bonding temperature of 300°C, AuSn2 IMC clusters, which were surrounded by AuSn4 IMC, were observed in the solder joint due to fast diffusivity of gold to molten solder with increased bonding temperature. Bond strength of gold stud bump joined with Sn3.5Ag solder was approximately 23 gf/bump, and fracture mode of the joint was intergranular cleavage between AuSn2 and AuSn4 IMCs. (13th Electronics Packaging Technology Conference, November 2011)

“Green Mold Compounds: Impact on Second Level Interconnect Reliability”

Authors: Bart VanDevelde, Melina Lofrano and Geert Willems; This e-mail address is being protected from spambots. You need JavaScript enabled to view it .
Abstract: So-called “green mold” compounds used in place of halogen flame retardants in plastic packages are often characterized by quartz filler, sometimes at levels topping 85%. High quartz levels lower the CTE, in some cases by more than half versus traditional mold compounds. The subsequent mismatch in thermal expansion between the package and printed circuit board is causing solder joint fatigue cracking, researchers found. The investigators are calling this failure mode “Cu lead fatigue fracture.” Other issues stem from the higher elastic modulus of the quartz-filled alternatives, which leads to more package stress. For their study, the researchers investigated two types of TSOPs. (13th Electronics Packaging Technology Conference, November 2011)

This column provides abstracts from recent industry conferences and company white papers. Our goal is to provide an added opportunity for readers to keep abreast of technology and business trends.

Last Updated on Wednesday, 01 February 2012 13:09
 

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